Semiconductor devices including transistors comprising a charge trapping material, and related systems and methods
A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.
1. A semiconductor device, comprising:
a memory storage component; and
a transistor in operable communication with the memory storage component, the transistor comprising:
a source region, a drain region, and a gate electrode between the source region and the drain region;
a charge trapping material surrounding at least an upper portion of vertically extending sidewalls of the gate electrode;
an oxide material on sides of the charge trapping material; and
another oxide material over at least a portion of the gate electrode, the another oxide material between the vertically extending sidewalls of the gate electrode and the charge trapping material and separating the charge trapping material from the gate electrode.
2. The semiconductor device of claim 1 , further comprising an array of transistors, wherein at least one transistor of the array of transistors comprises a greater density of trapped holes than other transistors of the array of transistors.
3. The semiconductor device of claim 2 , wherein the array of transistors comprises rows of transistors, wherein the at least one transistor is located in at least one row of the array of transistors comprising a greater density of trapped holes than transistors of other rows of transistors.
4. The semiconductor device of claim 1 , wherein the charge trapping material comprise silicon nitride.
5. The semiconductor device of claim 1 , wherein the gate electrode comprises polysilicon.
6. The semiconductor device of claim 1 , wherein:
the source region and the drain region are laterally offset from each other; and
the gate electrode is vertically offset from the source region and the drain region.
7. The semiconductor device of claim 1 , wherein the memory storage component comprises a capacitor.
8. The semiconductor device of claim 1 , wherein the oxide material comprises silicon dioxide, the gate electrode comprises polysilicon, and the charge trapping material comprises silicon nitride.
9. The semiconductor device of claim 1 , wherein the gate electrode comprises arcuate sidewalls.
10. The semiconductor device of claim 1 , wherein a lateral distance between the gate electrode and the oxide material varies along a vertical dimension of the gate electrode.
11. A method of forming a semiconductor device, the method comprising:
forming an oxide material on sidewalls of trenches in a semiconductive material;
forming a gate electrode material within the trenches;
forming another oxide material over at least a portion of the gate electrode material;
forming a charge trapping material in contact with the oxide material and the another oxide material, the charge trapping material surrounding at least an upper portion of vertically extending sidewalls of the gate electrode, the another oxide material between the vertically extending sidewalls of the gate electrode and the charge trapping material and separating the charge trapping material from the gate electrode;
forming a source region and a drain region on opposing sides of the trenches to form a transistor, the gate electrode between the source region and the drain region; and
forming a memory storage component in operable communication with the transistor.
12. The method of claim 11 , further comprising trapping a charge in the charge trapping material located within some of the trenches.
13. The method of claim 12 , wherein trapping a charge in the charge trapping material comprises exposing the gate electrode material associated with the charge trapping material to a voltage between about 4.0 V and about 5.0 V.
14. The method of claim 11 , wherein forming a gate electrode comprises forming a gate electrode comprising doped polysilicon within the trenches.
15. The method of claim 11 , wherein forming a charge trapping material comprises forming the charge trapping material comprising silicon nitride.
16. The method of claim 11 , wherein forming a memory storage component comprises forming a capacitor.
17. The method of claim 11 , wherein forming another oxide material comprises forming the another oxide material at a temperature below about 25° C.
18. The method of claim 11 , further comprising removing at least a portion of the gate electrode material to form a gate electrode material comprising arcuate sides.
19. A system, comprising:
at least one processor device operably coupled to at least one input device and at least one output device; and
a semiconductor device operably coupled to the at least one processor device, the semiconductor device comprising at least one memory cell comprising:
a memory storage element; and
a transistor, the transistor comprising:
a gate electrode within a base material;
an oxide material over at least a portion of the gate electrode;
a charge trapping material over the oxide material;
another oxide material over sides of the charge trapping material, the charge trapping material directly contacting the another oxide material and the oxide material, the charge trapping material separated from the gate electrode by the oxide material; and
a source region and a drain region on opposing sides of the gate electrode.
20. The system of claim 19 , wherein a distance between the gate electrode and the another oxide material varies along a length of the gate electrode.
21. The system of claim 19 , wherein a maximum distance between the gate electrode and the another oxide material is between about 5 nm and about 6 nm.
22. The system of claim 19 , wherein the oxide material exhibits a greater density than a density of the another oxide material.
23. The system of claim 19 , wherein the gate electrode comprises polysilicon, the oxide material comprises silicon dioxide, the charge trapping material comprises silicon nitride, and the another oxide material comprises silicon dioxide.
24. The system of claim 19 , wherein the source region, the oxide material, the charge trapping material, the another oxide material, and the gate electrode comprise a SONOS structure.
25. The semiconductor device of claim 1 , wherein the gate electrode is disposed in an upper portion of the transistor.
26. A semiconductor device, comprising:
a memory storage component; and
an array of transistors, at least one transistor of the array of transistors in operable communication with the memory storage component, the at least one transistor comprising:
a source region, a drain region, and a gate electrode between the source region and the drain region;
a charge trapping material surrounding at least an upper portion of the gate electrode; and
an oxide material on sides of the charge trapping material, wherein the at least one transistor comprises a greater density of trapped holes than other transistors or the array of transistors.
27. A system, comprising:
at least one processor device operably coupled to at least one input device and at least one output device; and
a semiconductor device operably coupled to the at least one processor device, the semiconductor device comprising at least one memory cell comprising:
a memory storage element; and
a transistor, the transistor comprising:
a gate electrode within a base material;
an oxide material over at least a portion of the gate electrode;
a charge trapping material over the oxide material;
another oxide material over sides of the charge trapping material, a maximum distance between the gate electrode and the another oxide material between about 5 nm and about 6 nm; and
a source region and a drain region on opposing sides of the gate electrode.