Apparatuses and methods for performing an in-place inversion using sensing circuitry

1. A system, comprising:

a processing resource; and

a memory device, external to the processing resource, and comprising an array of memory cells coupled to sensing circuitry comprising a sense amplifier latch and a compute component latch;

wherein the memory device is configured to, in association with executing instructions from the processing resource, perform an in-place inversion on a data value stored in the compute component latch such that an inverse of the data value is stored in the compute component latch without having activated an access line of the array to perform the in-place inversion; and

wherein the memory device comprises control circuitry configured to cause performance of the in-place inversion by controlling the sensing circuitry to:

place the inverse of the data value on a complementary pair of data lines to which the sensing circuitry is coupled;

disable the compute component latch;

while the compute component latch is disabled, enable the sense amplifier latch to store the inverse of the data value therein; and

while the sense amplifier latch is enabled:

enable a pass transistor; and

while the pass transistor is enabled, enable the compute component latch such that the inverse of the data value is stored therein.

2. The system of claim 1 , wherein the memory device is configured to, in association with executing the instructions, provide the inverse of the data value from the compute component latch to the processing resource.

3. The system of claim 1 , wherein the memory device is configured to use the inverse of the data value stored in the compute component latch to perform a subsequent logical operation between the inverse of the data value and a data value stored in the array, and wherein the subsequent logical operation is performed without transferring data external to the array and sensing circuitry.

4. The system of claim 1 , wherein the processing resource comprises a processor of a host.

5. The system of claim 4 , wherein the host comprises a motherboard.

6. The system of claim 1 , wherein the memory device is a processor-in-memory device.

7. The system of claim 1 , wherein the memory device comprises control circuitry configured to execute the instructions from the processing resource.

8. The system of claim 1 , wherein the system comprises a server system.

9. The system of claim 1 , wherein the memory device is a DRAM device.

10. The system of claim 1 , wherein the sensing circuitry comprises transistors formed on pitch with the memory cells of the array.

11. An apparatus, comprising:

a memory cell coupled to a pair of complementary data lines;

sensing circuitry comprising a first latch and a second latch coupled to the pair of complementary data lines; and

control circuitry configured to perform an in-place inversion operation on a data value stored in the first latch by:

enabling a pair of invert transistors to place an inverse of the data value on the pair of complementary data lines;

disabling the first latch;

while the first latch is disabled, enabling the second latch to store the inverse of the data value in the second latch; and

while the second latch is enabled:

enabling a pass transistor; and

while the pass transistor is enabled, enabling the first latch such that the inverse of the data value is stored therein.

12. The apparatus of claim 11 , wherein the pass transistor comprises a first node coupled to a node of one of the pair of invert transistors and a second node coupled to the first latch.

13. The apparatus of claim 12 , wherein the sensing circuitry comprises:

a sense amplifier comprising the second latch; and

a compute component comprising the first latch and the pair of invert transistors.

14. A method, comprising:

receiving a number of instructions from a processing resource; and

in association with executing the number of instructions on a memory device external to the processing resource, performing an in-place inversion on a data value stored in a compute component latch such that an inverse of the data value is stored in the compute component latch without having activated an access line of an array of memory cells of the memory device to perform the in-place inversion; and

wherein the memory device comprises sensing circuitry coupled to the array and comprising a sense amplifier latch and the compute component latch; and

wherein performing the in-place inversion comprises enabling a pair of inverting transistors to place the inverse of the data value on a pair of complementary data lines to which the sense amplifier latch is coupled via a pair of pass transistors.

15. The method of claim 14 , wherein performing the in-place inversion further comprises:

subsequently disabling the pair of inverting transistors;

disabling the compute component latch, and while the compute component latch is disabled, storing the inverse of the data value in the sense amplifier latch by enabling the sense amplifier latch;

enabling the pair of pass transistors; and

while the pair of pass transistors are enabled, enabling the compute component latch to copy the inverse of the data value from the sense amplifier latch to the compute component latch.

16. The method of claim 14 , further comprising subsequently performing a logical operation between the inverse data value stored in the compute component and a data value stored in a memory cell of the array, wherein the logical operation is performed without transferring data to the processing resource.

17. The method of claim 14 , further comprising, prior to performing the in-place inversion on the data value stored in the compute component latch, sensing the data value from a memory cell in the array into the sensing circuitry by activating an access line of the array to which the memory cell is coupled.