Memory cell sensing with storage component isolation
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be selected using a selection component that is in electronic communication with a sense amplifier and a ferroelectric capacitor of a ferroelectric memory cell. A voltage applied to the ferroelectric capacitor may be sized to increase the signal sensed during a read operation. The ferroelectric capacitor may be isolated from the sense amplifier during the read operation. This isolation may avoid stressing the ferroelectric capacitor which may otherwise occur due to the applied read voltage and voltage introduce by the sense amplifier during the read operation.
1. A method, comprising:
applying a first voltage to a memory cell during a read operation;
activating a sense component in electronic communication with the memory cell after applying the first voltage; and
reducing the first voltage to a second voltage while the memory cell is electrically connected with the sense component and simultaneously with activating the sense component.
2. The method of claim 1 , further comprising:
establishing an electrical connection between the memory cell and the sense component by applying a voltage to a word line of a selection component in electronic communication with the memory cell.
3. The method of claim 1 , further comprising:
selecting the memory cell for a write operation before selecting the memory cell for the read operation, wherein the second voltage applied during the read operation is greater than a voltage applied to the memory cell during the write operation.
4. The method of claim 1 , further comprising:
activating a selection component in electronic communication with the memory cell, wherein the memory cell is selected for the read operation based at least in part on activating the selection component.
5. The method of claim 4 , wherein activating the selection component comprises:
applying a third voltage to the selection component, wherein the third voltage is higher than the first voltage applied to a plate line of the memory cell.
6. The method of claim 1 , further comprising:
comparing a voltage output by the memory cell to a reference voltage based at least in part on activating the sense component; and
determining a logic state of the memory cell based at least in part on the comparison.
7. The method of claim 1 , further comprising:
writing a logic state to the memory cell based at least in part on applying a third voltage that is less than the first voltage applied to the memory cell.
8. The method of claim 7 , wherein the third voltage is applied to a plate line of the memory cell.
9. The method of claim 1 , further comprising:
interrupting an electrical connection between a digit line of the memory cell and the sense component.
10. The method of claim 9 , wherein interrupting the electrical connection comprises:
modifying a voltage applied to a selection component between the memory cell and the sense component after activating the sense component.
11. The method of claim 1 , further comprising:
sensing, at the sense component, a voltage based at least in part on charge transferred to the sense component from the memory cell via an electrical connection.