Apparatus for supplying power supply voltage to semiconductor chip including volatile memory cell
Disclosed herein is an apparatus that includes a first semiconductor chip including a memory cell array having a volatile memory cell and an access control circuit configured to perform a refresh operation on the volatile memory cell, and a second semiconductor chip including a power generator configured to supply a first power supply voltage to the first semiconductor chip. The access control circuit is configured to activate a first enable signal during the refresh operation. The second semiconductor chip is configured to change a capability of the power generator based on the first enable signal.
1. An apparatus comprising:
a first semiconductor chip including a memory cell array having a volatile memory cell and an access control circuit configured to perform a refresh operation on the volatile memory cell; and
a second semiconductor chip including a power generator configured to supply a first power supply voltage to the first semiconductor chip,
wherein the access control circuit is configured to activate a first enable signal during the refresh operation, and
wherein the second semiconductor chip is configured to change a capability of the power generator based on the first enable signal.
2. The apparatus of claim 1 ,
wherein the power generator includes first and second power generators coupled in parallel, and
wherein the second power generator is configured to activate when the first enable signal is activated.
3. The apparatus of claim 2 , wherein the first and second power generators are configured to activate when a second enable signal is activated regardless of the first enable signal.
4. The apparatus of claim 3 , further comprising a third semiconductor chip configured to generate the second enable signal.
5. The apparatus of claim 4 , wherein the first power generator has greater capability than the second power generator.
6. The apparatus of claim 5 ,
wherein the power generator further includes a third power generator coupled in parallel with the first and second power generators,
wherein the third power generator is configured to activate regardless of the first and second enable signals, and
wherein the second power generator has greater capability than the third power generator.
7. The apparatus of claim 1 , wherein the second semiconductor chip further includes a mode selector that invalidates the first enable signal.
8. The apparatus of claim 4 ,
wherein the second semiconductor chip further includes an additional power generator configured to supply a second power supply voltage to the first semiconductor chip via a power supply line, and
wherein the first enable signal is transferred from the first semiconductor chip to the second semiconductor chip via the power supply line.
9. The apparatus of claim 8 , wherein the additional power generator is configured to stop generating the second power supply voltage when the second enable signal is deactivated.
10. The apparatus of claim 9 ,
wherein the first semiconductor chip further includes an I/O circuit configured to output a data read from the memory cell array to the third semiconductor ship, and
wherein the I/O circuit is configured to operate on the second power supply voltage.
11. The apparatus of claim 10 ,
wherein the first semiconductor chip further includes a first switch circuit coupled between the power supply line and the I/O circuit and a second switch circuit coupled between the power supply line and the access control circuit, and
wherein the first and second switches are configured to exclusively turn on based on a command signal issued from the third semiconductor chip.