IP Library Granted Patent US 10,734,359
Granted Patent B2
US 10,734,359 · App. 16/108,644 · Granted Aug 4, 2020

Wiring with external terminal

Inventor: Hidenori Tobori (Sagamihara, JP)
Assignee: Micron Technology, Inc.
H01L25/0657H01L23/5226H01L23/5386H01L23/562
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Quick Facts
Patent No.
US 10,734,359
App. No.
16/108,644
Granted
Aug 4, 2020
Kind
B2
Abstract

Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes a first group of wiring layers of an internal redistributing layer (iRDL) providing a power supply voltage and a second group of wiring layers of another iRDL providing a ground voltage. The first group of wiring layers providing the power supply voltage from a first side of the semiconductor device to a second side of the semiconductor device opposite to the first side are at least partially separated by at least one cut portion between the first side and the second side.

Claims (68)

1. An apparatus comprising:

a semiconductor substrate defined by first and second sides opposite to each other;

a plurality of pads provided along the first side of the semiconductor substrate; and

a plurality of wiring layers including a plurality of groups of wiring layers, each group of wiring layers of the plurality of groups wiring layers extending from an associated one of the plurality of pads toward the second side of the semiconductor substrate,

wherein each group of wiring layers includes:

at least one cut portion between the first and second sides of the semiconductor substrate; and

wherein a first group of wiring layers of the plurality of groups of wiring layers completely separated by the cut portion and a second group of wiring layers of the plurality of groups of wiring layers partially separated by the cut portion.

2. The apparatus of claim 1 , further comprising a region where amplifier circuits are provided over the semiconductor substrate,

wherein the cut portion is provided over the region.

3. The apparatus of claim 1 , further comprising a region where logic circuits are provided over the semiconductor substrate,

wherein the cut portion is provided over the region.

4. The apparatus of claim 1 , wherein the first wiring layer and the second wiring layer are in a first layer and completely separated by the cut portion, and

wherein the first wiring layer and the second wiring layer are connected through a third wiring layer in a second layer different from the first layer.

5. The apparatus of claim 4 , wherein the first, second and the third wiring layers are arranged in line.

6. The apparatus of claim 1 , wherein the first group of plurality of wiring layers and the second group of plurality of wiring layers are arranged alternately and the first group of wiring layers are connected commonly to one another through a different layered wiring layer.

7. The apparatus of claim 1 , wherein the second group of wiring layers are connected commonly to one another by a same layered bridge.

8. The apparatus of claim 1 , wherein the each of the wiring layers are partially separated.

9. An apparatus comprising:

a semiconductor chip having a first side and a second side opposite the first side;

a power pad on the semiconductor chip along the first side and configured to receive a power supply voltage;

a plurality of wiring layers of a redistribution layer extending from the first side and the second side and configured to provide the power supply voltage from the power pad; and

a cut portion arranged between a first wiring layer of the plurality of wiring layers and a second wiring layer of the plurality of wiring layers, wherein the cut portion includes:

a metal layer different from the redistribution layer;

a first via coupling the first wiring layer and the metal layer; and

a second via coupling the second wiring layer and the metal layer,

wherein the first wiring layer is coupled to the metal layer and the second wiring layer is coupled to the metal layer.

10. The apparatus of claim 9 , wherein the cut portion further includes a bridge coupling the first wiring layer and the second wiring layer.

11. An apparatus comprising:

a semiconductor chip having a first side and a second side opposite the first side:

a power pad on the semiconductor chip along the first side and configured to receive a power supply voltage;

a plurality of wiring layers of a redistribution layer extending from the first side and the second side and configured to provide the power supply voltage from the power pad; and

a cut portion arranged between a first wiring layer of the plurality of wiring layers and a second wiring layer of the plurality of wiring layers, and the cut portion includes a bridge coupling the first wiring layer and the second wiring layer, wherein the plurality of wiring layers are a first group of wiring layers and the redistribution layer is a first redistribution layer, the apparatus further comprising:

a second group of wiring layers of a second redistribution layer extending from the first side and the second side, the second group of wiring layers including a third wiring layer and a fourth wiring layer,

wherein the first wiring layer and the third wiring layer are arranged in a first direction between the first side and the second side across the cut portion, and

wherein the second wiring layer and the fourth wiring layer are arranged in the first direction and parallel to the first wiring layer and the third wiring layer across the cut portion.

12. The apparatus of claim 11 , wherein the second group of wiring layers are configured to provide a ground voltage.

13. An apparatus comprising:

a semiconductor chip having a first side and a second side opposite the first side;

a power pad on the semiconductor chip along the first side and configured to receive a power supply voltage;

a plurality of wiring layers of a redistribution layer extending from the first side and the second side and configured to provide the power supply voltage from the power pad; and

a cut portion arranged between a first wiring layer of the plurality of wiring layers and a second wiring layer of the plurality of wiring layers,

wherein the first wiring layer and the second wiring layer are coupled by a wire having a width less than a width of the first wiring layer and the second wiring layer.

14. The apparatus of claim 13 , wherein the wire is between slits made of a passivation layer covering the first wiring layer and the second wiring layer.

15. The apparatus of claim 14 , wherein the passivation layer is made of polyimide.

16. The apparatus of claim 15 , wherein the redistribution layer is made of aluminum.

17. An apparatus comprising:

a substrate;

a first level wiring layer above the substrate;

a second level wiring layer above the first wiring layer;

a first side extending in a first direction;

a second side opposite to the first side extending in the first direction;

a third side longer than the first side and the second side, extending in a second direction perpendicular to the first direction;

a plurality of wiring layers of a redistribution layer in the second level wiring layer extending in the second direction, wherein the plurality of wiring layers includes a first wiring layer, a second wiring layer and a third wiring layer;

a first cut portion arranged between the first wiring layer and the second wiring layer the first cut portion including one of a logic circuit region, a decoder region and an amplifier region on the first metal layer; and

a second cut portion arranged between the second wiring layer and the third wiring layer, the second cut portion including one of the others of the logic circuit region, the decoder region and the amplifier region on the first metal layer.

18. The apparatus of claim 17 , wherein the first wiring layer and the second wiring layer are coupled to each other in the first level wiring layer.

19. The apparatus of claim 17 , wherein the first wiring layer and the second wiring layer are coupled to each other by a wire of the redistribution layer having a width less than a width of the first and second wiring layers.

20. An apparatus comprising:

a substrate;

a first level wiring layer above the substrate;

a second level wiring layer above the first wiring layer;

a first side extending in a first direction;

a second side opposite to the first side extending in the first direction;

a third side longer than the first side and the second side, extending in a second direction perpendicular to the first direction;

a plurality of wiring layers of a redistribution layer in the second level wiring layer extending in the second direction, wherein the plurality of wiring layers includes a first wiring layer, a second wiring layer and a third wiring layer;

a first cut portion arranged between the first wiring layer and the second wiring layer; and

a second cut portion arranged between the second wiring layer and the third wiring layer, wherein the first wiring layer and the third wiring layer are configured to provide a first power supply voltage, and

wherein the second wiring layer is configured to provide a second power supply voltage different from the first power supply voltage.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051028/0835 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050719/0550 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.., AS COLLATERAL AGENT
Reel/Frame 047630/0756 →
SUPPLEMENT NO. 10 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048102/0420 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2018
From: TOBORI, HIDENORI
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046662/0108 →
Cited By (1)
US 12,564,042