IP Library Granted Patent US 10,573,728
Granted Patent B2
US 10,573,728 · App. 16/108,899 · Granted Feb 25, 2020

Field effect transistors having a fin

Inventor: Toru Tanzawa (Tokyo, JP)
Assignee: Micron Technology, Inc.
H01L29/66795H01L29/0657H01L29/785H01L27/11286
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Quick Facts
Patent No.
US 10,573,728
App. No.
16/108,899
Granted
Feb 25, 2020
Kind
B2
Abstract

Transistors might include first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions.

Claims (14)

1. A transistor, comprising:

a first semiconductor fin;

a second semiconductor fin having a first side adjacent a first side of the first semiconductor fin;

a third semiconductor fin adjacent a second side of the first semiconductor fin;

a fourth semiconductor fin adjacent a second side of the second semiconductor fin;

a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin;

a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin;

a first conductive region in the third semiconductor fin and extending downward from an uppermost surface of the third semiconductor fin;

a second conductive region in the fourth semiconductor fin and extending downward from an uppermost surface of the fourth semiconductor fin;

a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins; and

a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions;

wherein the first semiconductor fin, the second semiconductor fin, the third semiconductor fin and the fourth semiconductor fin each have a first conductivity type;

wherein the first source/drain region and the second source/drain region each have a second conductivity type different than the first conductivity type; and

wherein the first conductive region and the second conductive region each have the first conductivity type.

Assignments (5)
CONFIRMATORY LICENSE Recorded Oct 23, 2023
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 065312/0710 →
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051028/0835 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050719/0550 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.., AS COLLATERAL AGENT
Reel/Frame 047630/0756 →
SUPPLEMENT NO. 10 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048102/0420 →