Memory device with reduced neighbor memory cell disturbance
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping element, and control circuit. The memory cell and clamping element can be both coupled to a digit line. The control circuit can be configured to cause the clamping element to clamp the voltage of the digit line for a period of time while the digit line driver is caused to bias the digit line at a voltage level sufficient to enable selection of the memory cell. In addition, the control circuit can be configured to cause the access line driver to bias an access line coupled to memory cell when the voltage of the digit line is at the voltage level sufficient to enable selection of the memory cell.
1. An apparatus, comprising:
a memory array comprising a first memory cell and a second memory cell coupled with a digit line; and
a control circuit coupled with the memory array, the control circuit configured to:
discharge a first charge from the digit line via the second memory cell during a first time period of an access operation; and
transfer a second charge to or from the first memory cell via the digit line during a second time period of the access operation, wherein a data state of the first memory cell is based at least in part on the second charge.
2. The apparatus of claim 1 , wherein the control circuit is further configured to:
isolate the second memory cell from the digit line during the second time period.
3. The apparatus of claim 1 , wherein the control circuit is further configured to:
bias the digit line during the first time period and the second time period.
4. The apparatus of claim 1 , wherein the control circuit configured to access the first memory cell is further configured to:
bias a word line that is coupled with the first memory cell during the second time period.
5. The apparatus of claim 4 , wherein the control circuit is further configured to:
bias the digit line to a first voltage that exceeds a first threshold voltage during the first time period, wherein the first voltage of the digit line is based at least in part on the first charge discharged from the digit line during the first time period; and
bias the digit line to a second voltage that exceeds the first threshold voltage during the second time period, wherein the second voltage of the digit line is based at least in part on the second charge transferred to or from the first memory cell during the second time period.
6. The apparatus of claim 1 , wherein the control circuit is further configured to:
determine the data state of the first memory cell based at least in part on the second charge; or
program the data state of the first memory cell based at least in part on the second charge.
7. The apparatus of claim 1 , wherein:
the memory array further comprises a third memory cell coupled with a second digit line different than the digit line, the third memory cell being different from the first memory cell and the second memory cell; and
the control circuit is further configured to:
bias the digit line during the first time period and the second time period, wherein a voltage is induced on the second digit line during the first time period based at least in part on biasing the digit line; and
discharge at least a portion of the voltage induced on the second digit line during the first time period.
8. The apparatus of claim 7 , wherein the control circuit is further configured to:
bias a first word line coupled with the second memory cell and the third memory cell during the second time period.
9. The apparatus of claim 1 , wherein the memory array further comprises a third memory cell coupled with the digit line, wherein the control circuit is further configured to:
discharge a third charge from the digit line via the third memory cell during a first time period of a second access operation.
10. A method, comprising:
biasing a digit line operatively coupled with a first memory cell and a second memory cell during a first portion and a second portion of an access operation;
discharging a first charge from the digit line via the second memory cell during the first portion of the access operation; and
transferring a second charge to or from the first memory cell via the digit line during the second portion of the access operation, wherein a data state of the first memory cell is based at least in part on the second charge.
11. The method of claim 10 , further comprising:
determining the data state of the first memory cell based at least in part on the second charge; or
programming the data state of the first memory cell based at least in part on the second charge.
12. The method of claim 10 , further comprising:
coupling the second memory cell with the digit line during the first portion of the access operation.
13. The method of claim 12 , further comprising:
isolating the second memory cell from the digit line during the second portion of the access operation.
14. The method of claim 10 , further comprising:
discharging, during the first portion of the access operation, a third charge from a second digit line via a third memory cell coupled with the second digit line, wherein a voltage is induced on the second digit line during the first portion of the access operation based at least in part on biasing the digit line.
15. The method of claim 10 , further comprising:
transferring a third charge from the digit line during a first portion of a second access operation via a third memory cell coupled with the digit line.
16. An apparatus, comprising:
a memory array comprising a first memory cell coupled with a first digit line and a second memory cell coupled with a second digit line; and
a control circuit coupled with the memory array, the control circuit configured to:
bias the first digit line during a first portion and a second portion of an access operation, wherein a voltage is induced on the second digit line during the first portion of the access operation based at least in part on biasing the first digit line;
discharge, during the first portion of the access operation, at least a portion of the voltage induced on the second digit line via the second memory cell; and
transfer, during the second portion of the access operation, a charge to or from the first memory cell via the first digit line, wherein a data state of the first memory cell is based at least in part on the charge.
17. The apparatus of claim 16 , further comprising:
a first word line coupled with the first memory cell to selectively couple the first memory cell to the first digit line; and
a second word line coupled with the second memory cell to selectively couple the second memory cell to the second digit line, wherein the first word line is different from the second word line.
18. The apparatus of claim 17 , wherein the control circuit is further configured to:
bias the second word line during the first portion of the access operation, wherein the at least the portion of the voltage induced on the second digit line is discharged via the second memory cell based at least in part on biasing the second word line.
19. The apparatus of claim 17 , wherein the control circuit is further configured to:
bias the first word line during the second portion of the access operation, wherein the charge is transferred to or from the first memory cell based at least in part on biasing the first word line.
20. The apparatus of claim 16 , wherein the memory array further comprises:
a third memory cell coupled with a third digit line, wherein the second digit line and the third digit line are adjacent to the first digit line, wherein a second voltage is induced on the third digit line during the first portion of the access operation based at least in part on biasing the first digit line, and
the control circuit is further configured to:
discharge, during the first portion of the access operation, at least a portion of the second voltage induced on the third digit line via the third memory cell.