Interconnect systems and methods using memory links to send packetized data between different data handling devices of different memory domains
System on a Chip (SoC) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ configuration of a data processing system two or more SoCs are coupled with one or more hybrid memory cubes (HMCs). The memory packets enable communication with local HMCs in a given SoC's memory domain. The system interconnect packets enable communication between SoCs and communication between memory domains. In a dedicated routing configuration each SoC in a system has its own memory domain to address local HMCs and a separate system interconnect domain to address HMC hubs, HMC memory devices, or other SoC devices connected in the system interconnect domain.
1. A method of conveying data with a data handling device, the method comprising:
originating, with a first data handling device associated with a first memory domain, packetized memory requests on a first memory link to a first memory device in the first memory domain associated with the first data handling device;
receiving, with the first data handling device, packetized system requests on a second memory link originating from a second data handling device in a second memory domain, the second memory link physically and logically the same as the first memory link; and
responding, with the first data handling device, to the packetized system requests.
2. The method of claim 1 , further comprising buffering data received with the packetized system requests on the first data handling device to define an address space for the packetized system requests to the first data handling device.
3. The method of claim 1 , further comprising buffering read data to be sent when responding to the packetized system requests to define an address space on the first data handling device.
4. The method of claim 1 , wherein the packetized memory requests sent and received on the second memory link between the first data handling device to the second data handling device are passed through a first memory hub between the first data handling device and the second data handling device.
5. The method of claim 4 , further comprising passing some packetized memory requests to additional data handling devices.
6. The method of claim 4 , wherein passing some packetized memory requests to additional data handling devices occur through a second memory hub coupled to the first memory hub via an inter-hub link.
7. The method of claim 6 , further comprising passing some of the packetized system requests from the second memory hub to one or more additional memory cube hubs.
8. The method of claim 7 , wherein the one or more additional memory cube hubs are arranged according to a ring topology.
9. The method of claim 7 , wherein the one or more additional memory cube hubs are arranged according to a modified ring topology.
10. The method of claim 7 , wherein the one or more additional memory cube hubs are arranged according to a mesh topology.
11. The method of claim 1 , further comprising passing some of the packetized memory requests from the first memory device in the first memory domain to another memory device in the second memory domain.
12. The method of claim 1 , further comprising passing some of the packetized memory requests from the first memory in the first memory domain to another memory in the first memory domain.
13. The method of claim 1 , wherein originating the packetized memory requests on the first memory link occurs through a data requestor endpoint of the first data handling device.
14. The method of claim 13 , wherein receiving the packetized system requests on the second memory link occurs through a data handling endpoint of the first data handling device that is separate from the data requestor endpoint.
15. The method of claim 4 , wherein originating packetized system requests on the second memory link of the first data handling device to the second data handling device includes cache coherency traffic.
16. The method of claim 15 , further comprising encoding cache coherency requests into memory atomic request packets.
17. A system, comprising:
a first data handling device in a first memory domain; and
a second data handling device in a second memory domain, wherein the first data handling device is configured to:
originate packetized memory requests on a first memory link to a first memory device in the first memory domain;
receive packetized system requests on a second memory link originating from the second data handling device, the second memory link physically and logically the same as the first memory link; and
respond to the packetized system requests.
18. The system of claim 17 , wherein the packetized system requests originating from the second data handling device are received by the first data handling device through the first memory device.
19. The system of claim 17 , wherein the packetized system requests originating from the second data handling device are received by the first data handling device through a first memory hub coupled between the first data handling device and the second data handling device.
20. The system of claim 17 , wherein each of the first data handling device and the second data handling device is a system on a chip.