Ultra high density metal-oxide-metal capacitor
View Patent ↗A capacitor includes a shallow trench isolation (STI) layer disposed on top of a substrate. The capacitor also includes a first dielectric layer disposed on top of the STI layer. The capacitor further includes a metallization diffusion (MD) layer disposed within both of the STI layer and the first dielectric layer.
1. A capacitor comprising:
a shallow trench isolation (STI) layer disposed on top of a substrate;
a first dielectric layer disposed on top of the STI layer; and
a metallization diffusion (MD) layer disposed between the STI layer and the first dielectric layer, the MD layer including a first conductive trace and a second conductive trace facing each other, a portion of the STI layer and a portion of the first dielectric layer disposed between the first conductive trace and the second conductive trace.
2. The capacitor of claim 1 , further comprising a metallization layer disposed on top of the first dielectric layer.
3. The capacitor of claim 2 , further comprising a plurality of vias connecting between the MD layer and the metallization layer.
4. The capacitor of claim 2 , wherein the MD layer has a depth that is larger than a depth of the metallization layer.
5. The capacitor of claim 3 , wherein the metallization layer comprises a plurality of conductive traces comprising:
a first set of conductive traces connected to a first terminal connector; and
a second set of conductive traces connected to a second terminal connector, wherein one of the first and the second terminal connector is connected to an anode, and the other one of the first and the second terminal connector is connected to a cathode.
6. The capacitor of claim 5 , wherein the first set of conductive traces is disposed interleaved with the second set of conductive traces.
7. The capacitor of claim 5 , wherein the MD layer comprises:
a third set of conductive traces connected to the first set of conductive traces through one or more first vias of the plurality of vias; and
a fourth set of conductive traces connected to the second set of conductive traces through one or more second vias of the plurality of vias.
8. The capacitor of claim 7 , further comprising a plurality of floating gates, wherein each conductive trace of the MD layer has two of the floating gates disposed by both side of the conductive trace.
9. The capacitor of claim 1 , wherein the STI layer has better dielectric quality and dielectric constant compared to the first dielectric layer.
10. A metal-oxide-metal (MOM) capacitor for a FinFET comprising:
a shallow trench isolation (STI) layer disposed above a substrate along a first direction;
a first dielectric layer disposed above the STI layer along the first direction; and
a metallization diffusion (MD) layer disposed between the STI layer and the first dielectric layer, the MD layer including a first conductive trace and a second conductive trace facing each other along a second direction traversing the first direction, a portion of the STI layer and a portion of the first dielectric layer disposed between the first conductive trace and the second conductive trace.
11. The MOM capacitor of claim 10 , further comprising a metallization layer disposed above the first dielectric layer along the first direction.
12. The MOM capacitor of claim 11 , further comprising a plurality of vias connecting between the MD layer and the metallization layer.
13. The MOM capacitor of claim 11 , wherein the metallization layer comprises a plurality of conductive traces comprising:
a first set of conductive traces electrically connected to a third conductive trace in the metallization layer through corresponding vias, the first set of conductive traces including the first conductive trace; and
a second set of conductive traces electrically connected to a fourth conductive trace in the metallization layer through corresponding vias, the second set of conductive traces including the second conductive trace.
14. The MOM capacitor of claim 13 , wherein the first set of conductive traces is disposed interleaved with the second set of conductive traces.
15. The MOM capacitor of claim 13 ,
wherein the third conductive trace and the fourth conductive trace extend along the first direction, wherein the third conductive trace and the fourth conductive trace separated from each other along a third direction traversing the first direction and the second direction.
16. The MOM capacitor of claim 15 , further comprising a plurality of floating gates, wherein each conductive trace of the MD layer has two of the floating gates disposed by both side of the conductive trace.
17. The MOM capacitor of claim 11 , wherein the MD layer has a depth along the first direction that is larger than a depth of the metallization layer along the first direction.
18. The MOM capacitor of claim 10 , wherein the STI layer has better dielectric quality and dielectric constant compared to the first dielectric layer.
19. A method of fabricating a capacitor, comprising:
forming a shallow trench isolation (STI) layer on top of a substrate;
forming a metallization diffusion layer including a first conductive trace and a second conductive trace facing each other, a portion of the STI layer disposed between a first portion of the first conductive trace and a first portion of the second conductive trace; and
forming a first dielectric layer on top of the STI layer and the metallization diffusion layer, a portion of the first dielectric layer disposed between a second portion of the first conductive trace and a second portion of the second conducive trace.
20. The method of claim 19 , further comprising forming a metallization layer on top of the first dielectric layer, wherein the metallization layer is connected to the metallization diffusion layer through one or more vias.