Memory devices configured to provide external regulated voltages
Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.
1. A memory system, comprising:
a power supply configured to provide a supply voltage having a first voltage level to a memory device;
the memory device including:
one or more external inputs configured to receive the supply voltage;
a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level;
one or more memories configured to receive the output voltage from the voltage regulator; and
one or more external outputs configured to receive the output voltage from the voltage regulator and to supply the output voltage to one or more connected devices; and
the one or more connected devices.
2. The memory system of claim 1 ,
wherein the supply voltage comprises a first supply voltage and a second supply voltage,
wherein the one or more external inputs are a first one or more external inputs,
further comprising a second one or more external inputs configured to receive the second supply voltage having a third voltage level different from the first voltage level, and
wherein the voltage regulator is further configured to receive the second supply voltage from the second one or more external inputs.
3. The memory system of claim 1 ,
wherein the output voltage comprises a first output voltage and a second output voltage,
wherein the one or more memories are configured to receive the second output voltage from the voltage regulator, and
wherein the one or more external outputs are configured to receive the first output voltage from the voltage regulator and to supply the first output voltage to the one or more connected devices.
4. The memory system of claim 3 ,
wherein the one or more external outputs are a first one or more external outputs,
wherein the one or more connected devices comprise first one or more connected devices and second one or more connected devices,
further comprising a second one or more external outputs, and
wherein the second one or more external outputs are configured to receive the second output voltage from the voltage regulator and to supply the second output voltage to the second one or more connected devices.
5. The memory system of claim 1 ,
wherein the voltage regulator comprises a first voltage regulator and a second voltage regulator,
wherein the output voltage comprises a first output voltage and a second output voltage,
wherein the one or more memories are configured to receive the first output voltage from the voltage regulator, and
wherein the one or more external outputs are configured to receive the second output voltage from the voltage regulator and to supply the second output voltage to the one or more connected devices.
6. The memory system of claim 1 , wherein the voltage regulator comprises a power management integrated circuit (PMIC) that includes one or more registers configured to store information corresponding to the output voltage.
7. The memory system of claim 6 , wherein the information comprises the second voltage level, a tolerance corresponding to the second voltage level, or a combination thereof.
8. The memory system of claim 6 , wherein the output voltage comprises a plurality of output voltages, and wherein the information comprises a corresponding voltage level for each of the plurality of output voltages, a tolerance corresponding to each of the plurality of output voltages, a first order in which the plurality of output voltages are powered up, first delays corresponding to the first order, a second order in which the plurality of output voltages are powered down, second delays corresponding to the second order.
9. The memory system of claim 6 , wherein the PMIC is configured to output the information in response to receiving a command from a connected host device.
10. The memory system of claim 6 , wherein the PMIC is configured to modify the information in response to receiving a command from a connected host device.
11. The memory system of claim 10 , wherein the PMIC is configured to modify the output voltage reading the stored the information.
12. The memory system of claim 10 , wherein the connected host device is a processor of the memory system.
13. The memory system of claim 12 , wherein the one or more external devices comprise the processor.
14. The memory system of claim 1 , wherein the memory device is a memory module, and wherein the one or more external inputs and the one or more external outputs are comprised by an edge connector of the memory module.
15. The memory system of claim 14 , wherein the memory module is a dual in-line memory module (DIMM).
16. The memory system of claim 1 ,
wherein the output voltage comprises a first output voltage and a second output voltage,
wherein the one or more memories comprise one or more volatile memories and one or more non-volatile memories,
wherein the one or more volatile memories are configured to receive the first output voltage from the voltage regulator, and
wherein the one or more non-volatile memories are configured to receive the second output voltage from the voltage regulator.
17. The memory system of claim 16 , wherein the memory device is a non-volatile dual in-line memory module (NVDIMM).
18. A method for operating a memory system, comprising:
providing a supply voltage having a first voltage level from a power supply to the memory device;
generating from the supply voltage, with a voltage regulator of the memory device, and output voltage having a second voltage level different than the first voltage level;
providing the output voltage to one or more memories of the memory device; and
providing the output voltage to one or more connected devices external to the memory device.
19. The method of claim 18 ,
wherein the output voltage comprises a first output voltage and a second output voltage,
wherein providing the output voltage to one or more memories of the memory device comprises providing the second output voltage to one or more memories of the memory device, and
wherein providing the output voltage to one or more connected devices external to the memory device comprises providing the first output voltage to one or more connected devices external to the memory device.
20. A memory system, comprising:
a power supply configured to provide a supply voltage having a first voltage level to a memory device;
the memory device including:
one or more external inputs configured to receive the supply voltage;
a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level;
one or more memories configured to receive the output voltage from the voltage regulator; and
one or more external outputs configured to receive the output voltage from the voltage regulator and to supply the output voltage to one or more connected devices; and
the one or more connected devices,
wherein the voltage regulator is further configured to modify the output voltage in response to receiving a command from a connected host device.