Apparatuses and methods for concurrently accessing different memory planes of a memory
Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).
1. A method, comprising:
receiving a plurality of memory command and address pairs at a memory, wherein each pair of the plurality of memory command and address pairs is associated with a different memory plane of the memory than another pair of the plurality of memory command and address pairs;
responsive to receiving the plurality of memory command and address pairs, configuring, for concurrent memory access operations, power circuits coupled to respective driver circuits of respective memory planes, each memory plane of the respective memory planes associated with a respective pair of the plurality of memory command and address pairs; and
retrieving, in parallel, data from each memory plane associated with the respective pair of the plurality of memory command and address pairs based on the configured power circuits during the concurrent memory access operations.
2. The method of claim 1 , wherein configuring, for the concurrent memory access operations, the power circuits coupled to the respective driver circuits of the respective memory planes comprises configuring the respective driver circuits of the respective memory planes.
3. The method of claim 2 , wherein configuring the respective driver circuits of respective memory planes comprises configuring, serially, a respective driver circuit of the driver circuits and a respective power circuit of the power circuits based on the respective pair of the plurality of memory command and address pairs.
4. The method of claim 2 , further comprising providing respective global voltages to each respective driver circuit associated with a corresponding memory plane of the respective memory planes.
5. The method of claim 1 , further comprising providing respective voltages along respective access lines from each respective driver circuit to the respective memory plane.
6. The method of claim 1 , wherein retrieving, in parallel, the data from each of the memory planes associated with the respective pair of plurality of memory command and address pairs comprises concurrently charging a respective bitline of each of the memory planes associated with the group of memory command and address pairs.
7. The method of claim 6 , wherein retrieving, in parallel, data from each of the memory planes associated with the respective pair of the plurality of memory command and address pairs further comprises concurrently sensing the data at each of the memory planes associated with the respective pair of the plurality of memory, command and address pairs.
8. The method of claim 7 , wherein retrieving, in parallel, data from each of the memory planes associated with the group of memory command and address pairs further comprises concurrently latching the data at a respective page buffer coupled to each of the memory planes associated with the respective pair of the plurality of memory command and address pairs.