IP Library Granted Patent US 10,761,739
Granted Patent B2
US 10,761,739 · App. 16/110,739 · Granted Sep 1, 2020

Multi-level wear leveling for non-volatile memory

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Quick Facts
Patent No.
US 10,761,739
App. No.
16/110,739
Granted
Sep 1, 2020
Kind
B2
Abstract

A memory sub-system performs a first wear leveling operation among a plurality of individual data units of the memory component after a first interval and performs a second wear leveling operation among a first plurality of groups of data units of the memory component after a second interval, wherein a first group of the first plurality of groups comprises the plurality of individual data units. The memory sub-system further performs a third wear leveling operation among a second plurality of groups of data units of the memory component after a third interval, wherein a second group of the second plurality of groups comprises the first plurality of groups of data units.

Claims (42)

1. A method comprising:

performing, by a processing device, a first wear leveling operation among a plurality of individual data units of a memory component after a first interval;

performing, by the processing device, a second wear leveling operation among a plurality of first-level groups of individual data units in a hierarchy of groups of the memory component after a second interval, wherein at least one first-level group of the plurality of first-level groups comprises the plurality of individual data units; and

performing, by the processing device, a third wear leveling operation among a plurality of second-level groups of data units of the memory component after a third interval, wherein at least one second-level group of the plurality of second-level groups comprises the plurality of first-level groups of individual data units.

2. The method of claim 1 , wherein the first interval is shorter than the second interval, and wherein the second interval is shorter than the third interval.

3. The method of claim 1 , wherein performing the first wear leveling operation among the plurality of individual data units comprises using a first algebraic mapping function, and wherein performing the second wear leveling operation among the plurality of first-level groups of data units comprises a second algebraic mapping function.

4. The method of claim 3 , wherein the second algebraic mapping function is different than the first algebraic mapping function.

5. The method of claim 3 , wherein performing the third wear leveling operation among the plurality of second-level groups of data units comprises using at least one of a third algebraic mapping function or indirect mapping.

6. The method of claim 5 , wherein using at least one of the first, second or third algebraic mapping functions comprises:

applying a first logical index associated with data to the at least one of the first, second or third algebraic mapping functions to determine a physical index corresponding to a physical location on the memory component; and

copying the data to the physical location.

7. The method of claim 5 , wherein using indirect mapping comprises:

copying data to an available physical location on the memory component; and

recording a mapping of a second logical index associated with the data to the available physical location in a look-up table.

8. The method of claim 1 , wherein the first, second and third intervals are based on at least one of a period of time that has elapsed since a previous wear leveling operation was performed or a number of data write operations performed on the memory component by a host machine since the previous wear leveling operation was performed.

9. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to:

perform a first wear leveling operation among a plurality of individual data units of the memory component after a first interval;

perform a second wear leveling operation among a plurality of first-level groups of individual data units in a hierarchy of groups of the memory component after a second interval, wherein at least one first-level group of the plurality of first-level groups comprises the plurality of individual data units; and

perform a third wear leveling operation among a plurality of second-level groups of data units of the memory component after a third interval, wherein at least one second-level group of the plurality of second-level groups comprises the first plurality of first-level groups of individual data units.

10. The system of claim 9 , wherein the memory component comprises a cross-point array of non-volatile memory cells.

11. The system of claim 9 , wherein the first interval is shorter than the second interval, and wherein the second interval is shorter than the third interval.

12. The system of claim 9 , wherein to perform the first wear leveling operation among the plurality of individual data units, the processing device to use a first algebraic mapping function, and wherein to perform the second wear leveling operation among the plurality of first-level groups of data units, the processing device to use a second algebraic mapping function.

13. The system of claim 12 , wherein the second algebraic mapping function is different than the first algebraic mapping function.

14. The system of claim 12 , wherein to perform the third wear leveling operation among the plurality of second-level groups of data units, the processing device to use at least one of a third algebraic mapping function or indirect mapping.

15. The system of claim 14 , wherein to use at least one of the first, second or third algebraic mapping functions, the processing device to:

apply a first logical index associated with data to the at least one of the first, second or third algebraic mapping functions to determine a physical index corresponding to a physical location on the memory component; and

copy the data to the physical location.

16. The system of claim 14 , wherein to use indirect mapping, the processing device to:

copy data to an available physical location on the memory component; and

record a mapping of a second logical index associated with the data to the available physical location in a look-up table.

17. The system of claim 9 , wherein the first, second and third intervals are based on at least one of a period of time that has elapsed since a previous wear leveling operation was performed or a number of data write operations performed on the memory component by a host machine since the previous wear leveling operation was performed.

18. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

detect an occurrence of a first trigger;

redistribute a plurality of individual data units to different physical locations on a memory component in response to the occurrence of the first trigger;

detect an occurrence of a second trigger;

redistribute a plurality of first-level groups of individual data units in a hierarchy of groups to different physical locations on the memory component in response to the occurrence of the second trigger, wherein at least one first-level group of the plurality of first-level groups comprises the plurality of individual data units;

detect an occurrence of a third trigger; and

redistribute a plurality of second-level groups of data units to different physical locations on the memory component in response to the occurrence of the third trigger, wherein at least one second-level group of the plurality of second-level groups comprises the plurality of first-level groups of individual data units.

19. The non-transitory computer-readable storage medium of claim 18 , wherein the second trigger occurs less frequently than the first trigger, and wherein third trigger occurs less frequently than the second trigger.

20. The non-transitory computer-readable storage medium of claim 18 , wherein to redistribute the plurality of individual data units, the processing device to use a first algebraic mapping function, wherein to redistribute the plurality of first-level groups of data units, the processing device to use a second algebraic mapping function, and wherein to redistribute the plurality of second-level groups of data units, the processing device to use at least one of a third algebraic mapping function or indirect mapping.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051028/0835 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050719/0550 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.., AS COLLATERAL AGENT
Reel/Frame 047630/0756 →
SUPPLEMENT NO. 10 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048102/0420 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2018
From: TAI, YING YU; CHEN, NING; ZHU, JIANGLI
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046686/0878 →