IP Library Granted Patent US 10,785,529
Granted Patent B2
US 10,785,529 · App. 16/110,740 · Granted Sep 22, 2020

Anticipatory video signal reception and processing

Inventor: Alexander G. Macinnis (Santa Clara, CA)
Assignee: Avago Technologies International Sales Pte. Limited
H04N21/4384H04N5/4401H04N5/50H04N7/163H04N21/4263H04N21/4312H04N21/4314H04N21/4382H04N21/44004H04N21/44222H04N21/4532H04N21/4623H04N21/4667H04N21/472H04N5/04H04N5/4403
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Quick Facts
Patent No.
US 10,785,529
App. No.
16/110,740
Granted
Sep 22, 2020
Kind
B2
Abstract

A system and method that provide reduced latency in a video signal processing system. Various aspects of the present invention may comprise receiving a current request from a user for first video information. Such a request may, for example, be received with a user interface module. A first video stream and a second video stream may be received simultaneously, where the first video stream comprises the first video information currently requested by the user, and the second video stream comprises second video information not currently requested by the user. A video receiver module may, for example, perform such receiving. The first video stream may be processed to present the first video information to the user at the current time. Further, the second video stream may be pre-processed in preparation for being presented to the user in the future. A video processing module may, for example, perform such video stream processing.

Claims (78)

1. An integrated circuit comprising:

one or more circuits configured to:

receive a plurality of video streams and process a first video stream of the plurality of video streams;

identify a second video stream of the plurality of video streams;

receive conditional access information for the second video stream; and

decrypt at least a portion of the second video stream responsive to receiving the conditional access information for the second video stream; and

a buffer configured to store the at least a portion of the second video stream using timing components of the second video stream that are tracked relative to timing components of the first video stream to control buffering activities for the second video stream to maintain an access point for decoding.

2. The integrated circuit of claim 1 , wherein the timing components of the second video stream comprise timestamp or synchronization components.

3. The integrated circuit of claim 1 , wherein the timing components of the second video stream are the same as the timing components of the first video stream.

4. The integrated circuit of claim 1 , wherein the second video stream includes video information and audio information.

5. The integrated circuit of claim 1 , wherein the one or more circuits configured to process the first video stream further comprises the one or more circuits configured to decode at least a portion of the first video stream.

6. The integrated circuit of claim 1 , wherein the second video stream is identified using at least one of genre video information, favorite video information, monitored user behavior information, or channel list information.

7. The integrated circuit of claim 1 , wherein the one or more circuits are further configured to:

identify a third video stream of the plurality of video streams;

receive conditional access information for the third video stream; and

responsive to receiving the conditional access information for the third video stream, decrypt at least a portion of the third video stream.

8. The integrated circuit of claim 1 , further comprising:

a video display driver circuit coupled to a video display.

9. An apparatus comprising:

a video receiver configured to receive a plurality of video streams;

one or more processing circuits configured to:

process a first video stream of the plurality of video streams;

identify a second video stream of the plurality of video streams;

receive conditional access information for the second video stream; and

responsive to receiving the conditional access information for the second video stream, decrypt at least a portion of the second video stream; and

a buffer configured to store the at least a portion of the second video stream using timing components of the second video stream that are related to a video display synchronization of the first video stream to control buffering activities for the second video stream to maintain an access point for decoding.

10. The apparatus of claim 9 , wherein the timing components of the second video stream comprise timestamp or synchronization components.

11. The apparatus of claim 9 , wherein the timing components of the second video stream are the same as timing components of the first video stream.

12. The apparatus of claim 9 , wherein the second video stream includes video information and audio information.

13. The apparatus of claim 9 , wherein the one or more processing circuits configured to process the first video stream further comprises the one or more processing circuits configured to decode at least a portion of the first video stream.

14. The apparatus of claim 9 , wherein the one or more processing circuits configured to process the first video stream further comprises the one or more processing circuits configured to process the first video stream for presentation, the apparatus further comprising:

a video display configured to display the first video stream.

15. The apparatus of claim 9 , wherein the second video stream is identified using at least one of genre video information, favorite video information, monitored user behavior information, or channel list information.

16. The apparatus of claim 9 , wherein the one or more processing circuits are further configured to:

identify a third video stream of the plurality of video streams;

receive conditional access information for the third video stream; and

decrypt at least a portion of the third video stream responsive to receiving the conditional access information for the third video stream.

17. The apparatus of claim 16 , wherein the one or more processing circuits are further configured to:

identify a fourth video stream of the plurality of video streams;

receive conditional access information for the fourth video stream; and decrypt at least a portion of the fourth video stream.

18. A system comprising:

a memory; and

a processor coupled to the memory, the processor configured to:

receive a plurality of video streams and process a first video stream of the plurality of video streams;

identify a second video stream of the plurality of video streams;

receive conditional access information for the second video stream;

decrypt at least a portion of the second video stream responsive to receiving the conditional access information for the second video stream; and

buffer the at least a portion of the second video stream using timing components of the second video stream that are tracked relative to timing components of the first video stream to control buffering activities for the second video stream to maintain an access point for decoding.

19. The system of claim 18 , wherein the timing components of the second video stream comprise timestamp or synchronization components.

20. The system of claim 18 , wherein the timing components of the second video stream are the same as the timing components of the first video stream.

21. The system of claim 18 , wherein the second video stream includes video information and audio information.

22. The system of claim 18 , wherein the processor configured to process the first video stream further comprises the processor configured to decode at least a portion of the first video stream.

23. The system of claim 18 , wherein the second video stream is identified using at least one of genre video information, favorite video information, monitored user behavior information, or channel list information.

24. The system of claim 18 , wherein the processor is further configured to:

receive a third video stream;

receive conditional access information for the third video stream; and

decrypt at least a portion of the third video stream responsive to receiving the conditional access information for the third video stream.

25. The system of claim 18 , further comprising: a video display configured to display the first video stream.

26. A system comprising:

one or more source provider devices configured to:

transmit a first video stream and a second video stream; and

transmit conditional access information for the first video stream and the second video stream; and

a video processing device configured to:

receive the first video stream and the second video stream;

process the first video stream;

identify the second video stream;

receive the conditional access information for the second video stream;

decrypt at least a portion of the second video stream responsive receiving the conditional access information for the second video stream; and

buffer the at least a portion of the second video stream using timing components of the second video stream that are related to a video display synchronization of the first video stream to control buffering activities for the second video stream to maintain an access point for decoding.

27. The system of claim 26 , wherein the timing components of the second video stream comprise timestamp or synchronization components.

28. The system of claim 26 , wherein the timing components of the second video stream are the same as timing components of the first video stream.

29. The system of claim 26 , wherein the second video stream includes video information and audio information.

30. The system of claim 26 ,

wherein the one or more source provider devices are further configured to transmit a third video stream and transmit conditional access information for the third video stream, and

wherein the video processing device is further configured to:

receive the third video stream;

receive the conditional access information for the third video stream; and

decrypt at least a portion of the third video stream responsive to receiving the conditional access information for the third video stream.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2020
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 052521/0578 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2020
From: MACINNIS, ALEXANDER G.
To: BROADCOM CORPORATION
Reel/Frame 052521/0707 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE OF THE MERGER AND APPLICATION NOS. 13/237,550 AND 16/103,107 FROM THE MERGER PREVIOUSLY RECORDED ON REEL 047231 FRAME 0369. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048549/0113 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047231/0369 →
Continuity (6)
Continuation 15676810 · Aug 14, 2017
Continuation 15255505 · Sep 2, 2016
Continuation 14492928 · Sep 22, 2014
Continuation 11046378 · Jan 28, 2005
Provisional Application 60556667 · Mar 26, 2004
Related Publication 20180367842A1 · Dec 20, 2018