IP Library Granted Patent US 10,665,782
Granted Patent B2
US 10,665,782 · App. 16/110,760 · Granted May 26, 2020

Methods of forming semiconductor structures including multi-portion liners

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Quick Facts
Patent No.
US 10,665,782
App. No.
16/110,760
Granted
May 26, 2020
Kind
B2
Abstract

A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.

Claims (26)

1. A method of forming a semiconductor device, the method comprising:

forming a protective portion of a liner on a top horizontal surface and sidewalls of stack structures, the protective portion comprising silicon nitride and the stack structures comprising chalcogenide materials and carbon materials, wherein forming the protective portion comprises forming the protective portion to have a varying thickness along the sidewalls of the stack structures; and

forming a conformal portion of the liner on the protective portion, the conformal portion comprising silicon carbonitride or silicon carboxynitride.

2. The method of claim 1 , wherein forming a protective portion of a liner comprises forming the silicon nitride of the protective portion of the liner by chemical vapor deposition.

3. The method of claim 1 , wherein forming a protective portion of a liner comprises forming the silicon nitride of the protective portion of the liner by plasma enhanced chemical vapor deposition.

4. The method of claim 1 , wherein forming a protective portion of a liner comprises forming the silicon nitride of the protective portion of the liner at a temperature of less than about 250° C.

5. The method of claim 1 , wherein:

forming a protective portion of a liner comprises forming the protective portion over only a portion of the sidewalls of the stack structures; and

forming a conformal portion of the liner comprises forming the conformal portion of the liner on the protective portion and over other portions of the sidewalls of the stack structures.

6. The method of claim 1 , wherein forming a protective portion of a liner comprises forming the protective portion over substantially all of the sidewalls of the stacks.

7. The method of claim 1 , wherein forming a conformal portion of the liner on the protective portion comprises forming the conformal portion at a temperature greater than a temperature used to form the protective portion.

8. The method of claim 1 , wherein forming a conformal portion of the liner on the protective portion comprises forming the conformal portion by atomic layer deposition.

9. The method of claim 1 , wherein forming a conformal portion of the liner on the protective portion comprises forming the conformal portion comprising a different amount of nitrogen than the silicon nitride of the protective portion.

10. A method of forming a semiconductor device, the method comprising:

forming a protective portion of a liner on at least a portion of stack structures, the protective portion comprising aluminum oxide (AlO x ), the stack structures comprising chalcogenide materials and carbon materials, and adjacent stack structures separated by openings; and

forming a conformal portion of the liner directly on and contacting the protective portion, the conformal portion of the liner comprising a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carboxynitride and the adjacent stack structures separated by the openings after forming the conformal portion of the liner.

11. The method of claim 10 , wherein forming a conformal portion comprises forming a portion of the conformal portion directly over and contacting the protective portion and at least another portion of the conformal portion directly on and contacting the stack structures.

12. The method of claim 10 , wherein forming a protective portion of a liner on at least a portion of stack structures comprises forming the protective portion as a substantially continuous material over substantially all of the stack structures.

13. The method of claim 12 , wherein forming the protective portion as a substantially continuous material over substantially all of the stack structures comprises separating the stack structures by smaller openings after forming the conformal portion of the liner.

14. The method of claim 10 , wherein forming a protective portion of a liner on at least a portion of stack structures comprises forming the protective portion by plasma enhanced chemical vapor deposition.

15. A method of forming a semiconductor device, the method comprising:

forming a protective portion of a liner on stack structures, the protective portion comprising silicon carbonitride or silicon carboxynitride and the stack structures comprising chalcogenide materials and carbon materials; and

forming a conformal portion of the liner directly on and contacting the protective portion, the conformal portion comprising aluminum oxide (AlO x ).

16. The method of claim 15 , further comprising densifying the conformal portion of the liner.

17. The method of claim 16 , wherein densifying the conformal portion of the liner comprises plasma treating the conformal portion of the liner.

18. The method of claim 16 , wherein densifying the conformal portion of the liner comprises heating the conformal portion of the liner.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051028/0835 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050719/0550 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.., AS COLLATERAL AGENT
Reel/Frame 047630/0756 →
SUPPLEMENT NO. 10 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048102/0420 →