Semiconductor device including a clock adjustment circuit
View Patent ↗Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.
1. An apparatus comprising:
a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation responsive to a first control signal; and
a timing generator configured to respond to a second control signal to adjust a frequency of the first control signal, wherein the timing generator is configured to terminate the phase control operation responsive to the second control signal indicating that the first and second clock signals are in phase,
wherein the timing generator comprises a detector configured to monitor a logical level of the second control signal, wherein the detector is configured to provide a third control signal responsive to a change in the logical level of the second control signal,
wherein the timing generator is further configured to provide a timing signal responsive to the third control signal, wherein the timing generator is further configured to adjust a frequency of the first control signal responsive to the third control signal at a logical high level, wherein the timing generator is further configured to adjust a frequency of the timing signal responsive to the third control signal at the logical high level, and wherein the timing generator is further configured to adjust the frequency of the first control signal based on an adjusted frequency of the timing signal.
2. The apparatus as claimed in claim 1 , wherein the timing generator is configured to receive the second control signal and to detect a state of the second control signal.
3. The apparatus as claimed in claim 1 , wherein the detector is further configured to detect a state of the second control signal, the state of the second control signal indicating whether the first and second clock signals are in phase or out of phase.
4. The apparatus as claimed in claim 3 , wherein the detector is configured to receive the timing signal, wherein a high logical level of the timing signal activates the first control signal.
5. The apparatus as claimed in claim 1 , further comprising:
a phase detector configured to produce the second control signal, the phase detector configured to receive the first and second clock signals.
6. The apparatus as claimed in claim 1 , wherein the phase control operation is performed in a manner of a DLL (Delay Locked Loop).
7. An apparatus comprising:
a clock circuit configured to receive first and second clock signals and perform a phase control operation for the first and second clock signals; and
a timing generator configured to assert a first control signal cyclically, the timing generator configured to respond to a second control signal to control a cycle of producing the first control signal, wherein the timing generator includes an enable signal generator that is configured to initiate the phase control operation responsive to a timing signal being activated, wherein the timing generator is configured to terminate the phase control operation responsive to the second control signal indicating that the first and second clock signals are in phase,
wherein the timing generator comprises a detector configured to monitor a logical level of the second control signal, wherein the detector is configured to provide a third control signal responsive to a change in the logical level of the second control signal,
wherein the timing generator is further configured to provide the timing signal responsive to the third control signal, wherein the timing generator is further configured to adjust a frequency of the first control signal responsive to the third control signal at a logical high level, wherein the timing generator is further configured to adjust a frequency of the timing signal responsive to the third control signal at the logical high level, and wherein the timing generator is further configured to adjust the frequency of the first control signal based on an adjusted frequency of the timing signal.
8. The apparatus as claimed in claim 7 , wherein the clock circuit comprises a comparator circuit configured to produce the second control signal that indicates, by keeping a logic state thereof unchanged, that the first and second clock signals are out of phase.
9. The apparatus as claimed in claim 7 , wherein the detector is further configured to activate the third control signal when the second control signal indicates that the first and second clock signals are out of phase over a period of at least two consecutive pulses of the first clock signal.
10. The apparatus as claimed in claim 9 , wherein the timing generator further comprises the enable signal generator configured to produce the first control signal in a first cycle during the third control signal being activated and in a second cycle during the third control signal being deactivated.
11. The apparatus as claimed in claim 10 , wherein the first cycle is smaller than the second cycle.
12. The apparatus as claimed in claim 7 , wherein the clock circuit is configured to initiate the phase control operation when the first control signal is asserted.
13. A method comprising:
initiating a phase control operation to control a phase relationship between first and second clock signals responsive to a first control signal;
adjusting a frequency of the first control signal responsive to a state of a second control signal;
terminating the phase control operation when the first and second clock signals are in phase;
monitoring a logical level of the second control signal;
providing a third control signal responsive to a change in the logical level of the second control signal; and
providing a timing signal responsive to the third control signal,
wherein adjusting the frequency of the first control signal responsive to the state of the second control signal comprises:
adjusting the frequency of the first control signal responsive to the third control signal being at a logical high level;
adjusting a frequency of the timing signal responsive to the third control signal being at the logical high level; and
adjusting the frequency of the first control signal based on the frequency of the timing signal being adjusted.
14. The method as claimed in claim 13 , further comprising:
producing the second control signal indicative of a phase difference between the first and second clock signals; and
detecting a state of the second control signal that indicates whether the first and second clock signals are in phase or out of phase.
15. The method as claimed in claim 13 , wherein the second control signal comprises a first state to indicate the first and second clock signals are in phase and a second state to indicate the first and second clock signals are out of phase.
16. The method as claimed in claim 13 , wherein monitoring the logical level of the second control signal comprises detecting whether the logical level of the second control signal falls below a threshold value to detect the change in the logical level of the second control signal.