IP Library Granted Patent US 11,068,365
Granted Patent B2
US 11,068,365 · App. 16/110,881 · Granted Jul 20, 2021

Data recovery within a memory sub-system without moving or processing the data through a host

Inventor: David G. Springberg (Fort Collins, CO)
Assignee: Micron Technology, Inc.
G06F11/2094G06F3/0646G06F11/2053G06F2201/805G06F2201/82
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Quick Facts
Patent No.
US 11,068,365
App. No.
16/110,881
Granted
Jul 20, 2021
Kind
B2
Abstract

A command to transfer data in a portion of a memory component to a recovery portion of a different memory component is received from a host system, wherein the portion of the memory component is associated with a portion of the memory component that has failed, and the data in the portion of the memory component is recovered and transferred to the recovery portion of the different memory component without moving or processing the data through the host system responsive to receipt of the command.

Claims (37)

1. A system, comprising:

a memory component of a memory sub-system;

a register to store an address range that is outside of an existing address range associated with the memory component, wherein the existing address range associated with the memory component comprises an address range used by a host system to access the memory component; and

a processing device, operatively coupled with the memory component, to:

receive, from the host system, a command to transfer data in a portion of the memory component to a recovery portion of a different memory component within the memory sub-system, wherein the portion of the memory component is associated with a portion of the memory component that has failed; and

recover and transfer, responsive to receipt of the command, the data in the portion of the memory component to the recovery portion of the different memory component without moving or processing the data through the host system by using an address within the address range that is outside of the existing address range associated with the memory component, wherein the address provides an indication that the data is to be recovered and transferred to the recovery portion of the different memory component within the memory sub-system.

2. The system of claim 1 , wherein the portion of the memory component is a redundant array of independent disks (RAID) stripe.

3. The system of claim 1 , wherein the processing device is to:

receive, from the host system, a command to transfer data in a portion of the memory component that has not failed; and

transfer, responsive to receipt of the command, the data in the portion of the memory component that has not failed to the recovery portion of the different memory component without moving or processing the data through the host system.

4. The system of claim 1 , wherein the processing device is to:

receive, from the host system, an additional command to transfer data in an additional portion of the memory component to an additional recovery portion of the different memory component, wherein the additional portion of the memory component is associated with an additional portion of the memory component that has failed; and

recover and transfer, responsive to receipt of the additional command and while recovering and transferring the data in the portion of the memory component to the recovery portion of the different memory component, the data in the additional portion of the memory component to the additional recovery portion of the different memory component without moving or processing the data through the host system.

5. The system of claim 1 , further comprising a switch operatively coupled with the memory component and the different memory component, and wherein the processing device is to recover and transfer the data in the portion of the memory component to the recovery portion of the different memory component using the switch.

6. The system of claim 1 , wherein the processing device is to send, to the host system, a notification of the failure of the portion of the memory component that has failed.

7. A method, comprising:

receiving, by a memory sub-system from a host system, a command to transfer data in a portion of a memory component of the memory sub-system to a recovery portion of a different memory component of the memory sub-system, wherein the portion of the memory component is associated with a portion of the memory component that has failed; and

recovering and transferring, by the memory sub-system responsive to receiving the command from the host system, the data in the portion of the memory component to the recovery portion of the different memory component without moving or processing the data through the host system by using an address within an address range that is outside of an existing address range associated with the memory component, wherein the existing address range associated with the memory component comprises an address range used by the host system to access the memory component and the address provides an indication that the data is to be recovered and transferred to the recovery portion of the different memory component within the memory sub-system.

8. The method of claim 7 , wherein recovering and transferring the data in the portion of the memory component to the recovery portion of the different memory component comprises performing an XOR operation on the data.

9. The method of claim 7 , further comprising recovering and transferring the data in the portion of the memory component to the recovery portion of the different memory component using a switch of the memory sub-system.

10. The method of claim 7 , wherein the portion of the memory component that has failed comprises all of the memory component.

11. The method of claim 7 , wherein the portion of the memory component that has failed comprises less than all of the memory component.

12. The method of claim 7 , further comprising sending a notification to the host system after recovering and transferring the data in the portion of the memory component to the recovery portion of the different memory component.

13. The method of claim 7 , further comprising:

receiving, by the memory sub-system from the host system, a command to transfer data in a portion of the memory component that has not failed; and

recovering and transferring, by the memory sub-system responsive to receipt of the command and while recovering and transferring the data in the portion of the memory component to the recovery portion of the different memory component, the data in the portion of the memory component that has not failed to an additional recovery portion of the different memory component without moving or processing the data through the host system.

14. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

receive, from a host system, an address range that is outside of an existing address range associated with a memory component, wherein the existing address range associated with the memory component comprises an address range used by the host system to access the memory component;

receive, from the host system, a command to transfer data in a redundant array of independent disks (RAID) stripe of the memory component to a recovery portion of the memory component, wherein the RAID stripe is associated with a portion of the memory component that has failed; and

recover and transfer, responsive to receipt of the command, the data in the RAID stripe of the memory component to the recovery portion of the memory component using an address within the received address range that is outside of the existing address range associated with the memory component, wherein the address provides an indication that the data is to be recovered and transferred to the recovery portion of the memory component within the memory component, such that the data is recovered and transferred without moving or processing the data through the host system.

15. The non-transitory computer-readable storage medium of claim 14 , wherein the processing device is further caused to store the received address range in a register.

16. The non-transitory computer-readable storage medium of claim 14 , wherein the processing device is further caused to:

change, after recovering and transferring the data in the RAID stripe of the memory component to the recovery portion of the memory component, an address associated with the recovered and transferred data to an address within the existing address range associated with the memory component.

17. The non-transitory computer-readable medium of claim 14 , wherein the recovery portion of the memory component comprises one of a plurality of recovery portions of the memory component.

18. The non-transitory computer-readable medium of claim 14 , wherein the command from the host system comprises:

an identification of the RAID stripe of the memory component; and

an identification of the recovery portion of the memory component.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051028/0835 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050719/0550 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.., AS COLLATERAL AGENT
Reel/Frame 047630/0756 →
SUPPLEMENT NO. 10 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048102/0420 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2018
From: SPRINGBERG, DAVID G.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046687/0724 →
Continuity (1)
Related Publication 20200065204A1 · Feb 27, 2020
Cited By (2)
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