Performing logical operations using sensing circuitry
View Patent ↗Apparatuses and methods related to performing logical operations using sensing circuitry are provided. One apparatus comprises an array of memory cells, sensing circuitry coupled to the array of memory cells via a sense line, and a controller coupled to the array of memory cells and the sensing circuitry. The sensing circuitry includes a sense amplifier and does not include an accumulator. The controller is configured to perform logical operations using the array of memory cells as an accumulator without transferring data out of the memory array and sensing circuitry.
1. A system, comprising:
a host configured to generate instructions;
a memory device coupled to the host and comprising an array of memory cells configured to store operands; and
control circuitry configured to execute instructions from the host by causing logical operations to be performed on operands stored in memory cells corresponding to a same column and coupled to different access lines of the array;
wherein the logical operations are performed without transferring the operands to the host, by using the array as an accumulator.
2. The system of claim 1 , wherein the host comprises a processing resource configured to generate the instructions.
3. The system of claim 2 , wherein the processing resource comprises a host processor.
4. The system of claim 2 , wherein the processing resource comprises a controller.
5. The system of claim 1 , wherein the control circuitry comprises a state machine.
6. The system of claim 1 , wherein the control circuitry comprises a sequencer.
7. The system of claim 1 , wherein the control circuitry comprises a shift controller configured to control shifting data in the array.
8. The system of claim 1 , wherein the host comprises a processor, and wherein the processor is on a separate integrated circuit from an integrated circuit on which the memory device is located.
9. The system of claim 1 , wherein the host and the memory device are on a same integrated circuit.
10. The system of claim 1 , wherein the host comprises a processing resource configured to perform logical operations in addition to those logical operations performed on the memory device.
11. The system of claim 1 , further comprising a control bus configured to provide signals from the host to be decoded by the control circuitry.
12. The system of claim 1 , wherein the system is a server system.
13. The system of claim 1 , wherein the host comprises a motherboard and/or backplane.
14. The system of claim 1 , wherein the system has a Von Neumann architecture.
15. A system, comprising:
a host configured to generate instructions;
a memory device coupled to the host and comprising an array of memory cells configured to store operands; and
control circuitry configured to execute instructions from the host by causing logical operations to be performed, using the array as an accumulator, on operands stored in memory cells of the array;
wherein a least one operand of the logical operations is stored in array throughout performance of the logical operations.
16. The system of claim 15 , wherein the memory device comprises a processor-in-memory device coupled to the host via a bus, and wherein the host comprises a processor configured to perform logical operations in addition to logical operations performed using the array as the accumulator.
17. The system of claim 15 , wherein the control circuitry is local to the memory device and external to the host.
18. A method, comprising:
generating instructions on a host coupled to a memory device comprising an array of memory cells; and
executing the instructions using control circuitry of the memory device, wherein executing the instructions comprises causing performance of logical operations on operands stored in the array, without transferring the operands to the host, by using the array as an accumulator;
wherein the operands are stored in memory cells corresponding to a same column and coupled to different access lines of the array.
19. The method of claim 18 , further comprising providing the instructions from the host to the control circuitry via a control bus.
20. The method of claim 18 , further comprising providing control signals to shift circuitry of the array to shift data within the array.