Apparatuses and methods for cache invalidate

1. An apparatus, comprising:

a bit vector operation capable memory device configured to;

convert a bit vector bit length to a number of cache lines to be invalidated; and

generate a bulk invalidate command according to a cache coherency protocol of a cache memory system, wherein the bulk invalidate command uses the number of cache lines to be invalidated as an argument, wherein generating the bulk invalidate command, comprises:

providing a base address and the number of cache lines to be invalidated as an argument in packet fields sent to the cache memory system.

2. The apparatus of claim 1 , wherein the apparatus is further configured to convert an address of the bit vector to a cache line sized address relevant to the cache memory system, wherein the bulk invalidate command uses the cache line sized address as a base address and wherein converting the address of the bit vector comprises performing a logical AND operation using the address of the bit vector and a mask.

3. The apparatus of claim 1 , the bit vector operation capable memory device, comprising:

an array of memory cells;

sensing circuitry coupled to the array, the sensing circuitry including sense amplifiers and a compute component configured to implement logical operations; and

a memory controller coupled to the array and sensing circuitry, the memory controller configured to receive the bit vector based operation request.

4. The apparatus of claim 1 , wherein:

the bit vector based operation request is associated with a processor in memory (PIM) command; and

a bit vector based operation is a PIM operation.

5. The apparatus of claim 1 , wherein a channel controller is configured to generate the bulk invalidate command, the bulk invalidate command comprising a base address and a length expressed as a number of cache lines.

6. The apparatus of claim 1 , wherein the cache memory system has a MESI (modified, exclusive, shared, invalid) cache coherency protocol.

7. The apparatus of claim 1 , wherein the cache memory system has a directory based cache coherency protocol.

8. The apparatus of claim 1 , wherein the channel controller is configured to send the bulk invalidate command to all cache levels in the cache memory system.

9. The apparatus of claim 1 , wherein the channel controller is configured to send the bulk invalidate command to a last level cache (LLC) in the cache memory system and the LLC further sends to another level of cache memory according to a directory based cache coherency protocol.

10. The apparatus of claim 1 , wherein an invalidate engine associated with the LLC is configured to further send the bulk invalidate command to another level of cache memory.

11. The apparatus of claim 1 , wherein the channel controller is configured to send the bulk invalidate command to multiple cache levels in the cache memory system.

12. The apparatus of claim 1 , wherein the channel controller is configured receive a processor in memory (PIM) bit vector operation request and further configured to generate the bulk invalidate command from a base address length associated with a bit vector to be used in the PIM bit vector operation.

13. The apparatus of claim 1 , wherein the channel controller is configured to convert the length of the bit vector to a number of cache lines relevant to a cache line sized address in the cache memory system.

14. An apparatus, comprising:

a channel controller configured to:

receive a bit vector operation request; and

send a bulk invalidate command to a cache memory system responsive to receiving the bit vector operation request to free up space in the cache memory system for use by a bit vector operation;

modify a behavior of a cache coherency protocol associated with the cache memory system for responses to caching requests; and

allow read access to an invalidated portion of the cache memory system while the bit vector operation is being performed.

15. The apparatus of claim 14 , wherein the channel controller is further configured to track the bit vector operation performed responsive to receiving the bit vector operation request.

16. The apparatus of claim 14 , wherein modify the behavior comprises:

temporarily denying exclusive access or update requests to an invalidated portion of the cache memory system while the bit vector operation is being performed.

17. The apparatus of claim 14 , wherein modify the behavior comprises:

suspending exclusive access or update requests to an invalidated portion of the cache memory system until the bit vector operation is complete or can be interrupted.

18. The apparatus of claim 14 , wherein modify the behavior comprises:

adding meta data to the cache coherency protocol of the cache memory system; and

marking a cache line as in-use elsewhere and not shared.