Transistors comprising two-dimensional materials and related semiconductor devices, systems, and methods

1. A transistor, comprising:

a channel region comprising a two-dimensional material on a material, the channel region comprising opposing sidewalls separated by a seed material and oriented perpendicular to the material, the seed material comprising a crystalline aluminum oxide, gallium nitride, aluminum nitride, boron nitride, graphene, or combinations thereof;

a gate dielectric on the two-dimensional material; and

gates on the gate dielectric.

2. The transistor of claim 1 , wherein the transistor is configured in a vertical orientation.

3. The transistor of claim 1 , wherein the two-dimensional material comprises a thickness of from about one monolayer to about three monolayers.

4. The transistor of claim 1 , wherein a cross-section of the channel region comprises a substantially L-shape.

5. The transistor of claim 1 , wherein a cross-section of the channel region comprises two portions separated from one another.

6. The transistor of claim 1 , wherein the opposing sidewalls of the channel region are in direct contact with the gate dielectric.

7. The transistor of claim 1 , wherein the two-dimensional material comprises a single crystalline material selected from the group consisting of a transition metal dichalcogenide (TMDC), graphene, graphene oxide, stanene, phosphorene, hexagonal boron nitride (h-BN), borophene, silicone, graphyne, germanene, germanane, a 2D supracrystal, and combinations thereof.

8. The transistor of claim 7 , wherein the two-dimensional material comprises the TMDC comprising molybdenum sulfide (MoS 2 ), molybdenum selenide (MoSe 2 ), molybdenum telluride (MoTe 2 ), tungsten sulfide (WS 2 ), tungsten selenide (WSe 2 ), tungsten telluride (WTe 2 ), niobium sulfide (NbS 2 ), niobium selenide (NbSe 2 ), niobium telluride (NbTe 2 ), zirconium sulfide (ZrS 2 ), zirconium selenide (ZrSe 2 ), zirconium telluride (ZrTe 2 ), hafnium sulfide (HfS 2 ), hafnium selenide (HfSe 2 ), hafnium telluride (HfTe 2 ), rhenium sulfide (ReS 2 ), rhenium selenide (ReSe 2 ), rhenium telluride (ReTe 2 ), or combinations thereof.

9. The transistor of claim 1 , wherein the opposing sidewalls are separated from one another and oriented perpendicular to the material.

10. A semiconductor device, comprising:

memory cells, at least one memory cell of the memory cells comprising at least one vertical transistor and a storage element in operative communication with the at least one vertical transistor, the at least one vertical transistor comprising:

two substantially L-shaped channel regions comprising a two-dimensional material, the two substantially L-shaped channel regions in direct contact with a seed material;

a gate dielectric in direct contact with the two substantially L-shaped channel regions; and

gates on the gate dielectric.

11. The transistor of claim 10 , wherein the seed material comprises a crystalline aluminum oxide, gallium nitride, aluminum nitride, boron nitride, graphene, or combinations thereof.

12. The transistor of claim 11 , wherein the seed material directly contacts each of the opposing sidewalls of the channel region.

13. The transistor of claim 11 , wherein the seed material is oriented perpendicular to the material.

14. The semiconductor device of claim 10 , wherein the seed material comprises a crystalline aluminum oxide material.

15. The semiconductor device of claim 14 , wherein the crystalline aluminum oxide material is configured as a pillar separating the two substantially L-shaped channel regions.

16. A method of forming a semiconductor device, the method comprising:

forming a crystalline aluminum oxide on a material;

forming a two-dimensional material over the crystalline aluminum oxide, the two-dimensional material comprising opposing sidewalls;

forming a gate dielectric material over the two-dimensional material; and

forming gates on the gate dielectric material.

17. The method of claim 16 , wherein forming a crystalline aluminum oxide on a material comprises forming a pillar of crystalline aluminum oxide on the material by a wafer bonding and transfer method.

18. The method of claim 17 , wherein forming a pillar of crystalline aluminum oxide on the material comprises forming a crystalline aluminum oxide material on the material and patterning the crystalline aluminum oxide material.

19. The method of claim 16 , wherein forming a two-dimensional material over the crystalline aluminum oxide comprises conformally forming the two-dimensional material over the crystalline aluminum oxide and forming a gate dielectric material over the two-dimensional material comprises conformally forming the gate dielectric material over the two-dimensional material.

20. The method of claim 16 , further comprising removing horizontally oriented portions of the gate dielectric material and the two-dimensional material.

21. The method of claim 20 , wherein removing horizontally oriented portions of the two-dimensional material comprises forming a channel region comprising two portions of the two-dimensional material separated by the crystalline aluminum oxide.

22. The method of claim 20 , wherein removing horizontally oriented portions of the gate dielectric material and the two-dimensional material comprises forming sidewalls of a gate dielectric aligned with lateral edges of the two-dimensional material.

23. The method of claim 20 , wherein removing horizontally oriented portions of the gate dielectric material and the two-dimensional material comprises removing the horizontally oriented portions of the gate dielectric material and the two-dimensional material such that top surfaces of the crystalline aluminum oxide, the two-dimensional material, and the gate dielectric material are substantially coplanar with one another.

24. The method of claim 23 , further comprising removing the crystalline aluminum oxide.

25. The method of claim 24 , further comprising forming a dielectric material in place of the removed crystalline aluminum oxide.

26. A system, comprising:

memory cells comprising at least one transistor and a storage element in operative communication with the at least one transistor, the at least one transistor comprising:

a channel region comprising a two-dimensional material comprising opposing sidewalls, the two-dimensional material comprising a width of from about one monolayer of atoms to about three monolayers of atoms and oriented perpendicular to an underlying metal;

a seed material between the opposing sidewalls of the channel region;

a gate dielectric laterally adjacent the channel region; and

gates laterally adjacent the gate dielectric; and

a processor in operative communication with at least one input device, at least one output device, and the memory cells.

27. The system of claim 26 , wherein each of the opposing sidewalls of the channel region directly contacts a pillar of the seed material.

28. A transistor, comprising:

a channel region comprising a two-dimensional material on a material, the two-dimensional material comprising graphene, graphene oxide, stanene, phosphorene, hexagonal boron nitride (h-BN), borophene, silicone, graphyne, germanene, germanane, a 2D supracrystal, or combinations thereof, the channel region comprising two portions of the two-dimensional material oriented substantially perpendicular to the material and top surfaces of the two portions of the two-dimensional material substantially coplanar with a top surface of a pillar material between the two portions of the two-dimensional material;

a gate dielectric adjacent to the two-dimensional material; and

gates adjacent to the gate dielectric.

29. The transistor of claim 28 , wherein the two portions of the two-dimensional material comprise discrete portions of the two-dimensional material.

30. A transistor, comprising:

channel regions comprising a two-dimensional material on a material, opposing sidewalls of the channel regions separated by a dielectric material and the dielectric material in direct contact with the channel regions and portions of the channel regions exhibiting a substantially L-shape in cross-section;

a gate dielectric adjacent to the two-dimensional material, sidewalls of the gate dielectric substantially aligned with lateral edges of the channel regions; and

gates adjacent to the gate dielectric.

31. The transistor of claim 30 , wherein the dielectric material is oriented perpendicular to the material.

32. The transistor of claim 30 , wherein the dielectric material is configured as a pillar separating the channel regions.

33. The transistor of claim 30 , wherein the channel regions are on opposing sidewalls of the dielectric material.

34. The transistor of claim 30 , wherein the portions of the channel regions exhibiting the substantially L-shape in cross-section are separated from one another.