Semiconductor structure and manufacturing method for the same
View Patent ↗The present disclosure provides a semiconductor structure, including a bottom terminal, a first middle terminal over the bottom terminal and separated from the bottom terminal by a high-k dielectric layer, a second middle terminal over the first middle terminal and separated from the first middle terminal by the high-k dielectric layer, a top terminal over the second middle terminal and separated from the second middle terminal by the high-k dielectric layer, a first via penetrating the bottom terminal and the second middle terminal, a second via penetrating the first middle terminal, a first passivation layer below the bottom terminal, and a second passivation layer over the top terminal.
1. A semiconductor structure, comprising:
a bottom terminal;
a first middle terminal over the bottom terminal and separated from the bottom terminal by a high-k dielectric layer;
a second middle terminal over the first middle terminal and separated from the first middle terminal by the high-k dielectric layer;
a top terminal over the second middle terminal and separated from the second middle terminal by the high-k dielectric layer;
a first via penetrating the bottom terminal and the second middle terminal;
a second via penetrating the first middle terminal;
a first passivation layer below the bottom terminal;
a second passivation layer over the top terminal;
a conductive post over the first via; and
a third passivation layer over the second passivation layer and laterally surrounding the conductive post, wherein a top surface of the third passivation layer is above a top surface of the conductive post.
2. The semiconductor structure of claim 1 , further comprising at least one third middle terminal between the top terminal and the second middle terminal.
3. The semiconductor structure of claim 1 , wherein the first via and the second via are filled with a conductive material.
4. The semiconductor structure of claim 3 , wherein the conductive material comprises aluminum-copper.
5. The semiconductor structure of claim 1 , wherein a thickness of the first passivation layer is in a range from about 2,700 Angstrom to about 3,300 Angstrom.
6. The semiconductor structure of claim 1 , further comprising an etch stop layer above the second passivation layer.
7. The semiconductor structure of claim 1 , further comprising a first metal line below the first passivation layer.
8. A semiconductor structure, comprising:
a bottom terminal;
a first middle terminal over the bottom terminal and separated from the bottom terminal by a high-k dielectric layer;
a top terminal over the first middle terminal and separated from the first middle terminal by the high-k dielectric layer;
a first etch stop layer above the top terminal;
a passivation layer between the top terminal and the first etch stop layer;
a second etch stop layer above the first etch stop layer;
a dielectric layer between the first etch stop layer and the second etch stop layer;
a first via penetrating the bottom terminal, wherein the first via is filled with cobalt;
a cobalt post over the first via;
a seed layer spacing between the dielectric layer and a sidewall of the cobalt post, wherein the seed layer is in direct contact with a first portion of a top surface of the passivation layer free from being under a coverage of a vertical projection area of the second etch stop layer; and
a second via penetrating the first middle terminal.
9. The semiconductor structure of claim 8 , further comprising at least one second middle terminal between the first middle terminal and the top terminal.
10. The semiconductor structure of claim 8 , wherein the dielectric layer comprises oxides.
11. The semiconductor structure of claim 8 , further comprising a copper line under the bottom terminal.
12. The semiconductor structure of claim 11 , further comprising an undoped silicate glass (USG) layer between the copper line and the bottom terminal.
13. The semiconductor structure of claim 8 , wherein the first portion of the top surface of the passivation layer overlaps with the first middle terminal.
14. A semiconductor structure, comprising:
a bottom terminal;
a first middle terminal over the bottom terminal;
a top terminal over the first middle terminal;
a first passivation layer over the top terminal;
a second passivation layer above the first passivation layer;
a high-k dielectric layer between the bottom terminal and the first middle terminal, and between the first middle terminal and the top terminal;
a first via penetrating the bottom terminal and the high-k dielectric layer; and
a conductive post surrounded by the second passivation layer and above the first via, wherein a top surface of the second passivation layer is above a top surface of the conductive post.
15. The semiconductor structure of claim 14 , further comprising a second middle terminal between the top terminal and the first middle terminal.
16. The semiconductor structure of claim 14 , further comprising a second via penetrating the first middle terminal.
17. The semiconductor structure of claim 14 , further comprising:
a third passivation layer below the bottom terminal; and
a second etch stop layer above the second passivation layer.
18. The semiconductor structure of claim 17 , wherein the third passivation layer comprises one of the undoped silicate glass or plasma enhanced deposited oxide (PEOX).
19. The semiconductor structure of claim 14 , wherein a width of the conductive post is greater than a width of the first via.
20. The semiconductor structure of claim 14 , wherein the high-k dielectric layer comprises a tri-layer of zirconium oxide-aluminum oxide-zirconium oxide.