Successive approximation analog-to-digital converter with nonlinearity compensation
Successive-approximation-register (SAR) analog-to-digital conversion technique continues to be one of the most popular analog-to-digital conversion techniques, due to their versatility, which allows providing high resolution output or high conversion rates. In addition, SAR analog-to-digital converters (ADC) have a modest circuit complexity that results in low-power dissipation. A SAR ADC is, typically, composed of a single comparator, a bank of capacitors and switches, in addition to, a control digital logic. However, the comparator input capacitance is input-signal dependent, and hence introduces non-linearity to the transfer characteristics of the ADC. A simple technique is devised to significantly reduce this non-linearity, by pre-distorting the sampled-and-held input signal using the same comparator input capacitance.
1. A method of converting an analog signal to a digital signal using successive approximation, using circuitry comprising a sampling unit, a capacitor array, a sampling capacitor, a comparator, a successive approximation register and control logic, wherein, the method comprising:
during a sampling phase that ends at a sampling edge, coupling the sampling capacitor to an input voltage and powering off the comparator;
during a hold phase that begins at the sampling edge, de-coupling the sampling capacitor from the input voltage with the comparator powered off;
during a pre-distortion phase subsequent to the hold phase and before a bit cycling phase, powering on the comparator with the sampling capacitor de-coupled from the input voltage,
such that distortion caused by input capacitance variations of the comparator is reduced; and
during the bit-cycling phase subsequent to the pre-distortion phase, coupling the sampling capacitor to a reference voltage with the comparator powered on.
2. An analog to digital converter for converting an analog signal to a digital signal using successive approximation, wherein the analog to digital converter is configured to provide a pre-distortion phase, following a sampling phase and prior to a bit-cycling phase, comprising:
a sampling unit for sampling an analog input signal to produce a sampled signal;
a capacitor array coupled to the sampling unit for producing an approximation signal;
a comparator coupled to the capacitor array for comparing the approximation signal to the sampled signal; and
a successive approximation register and control logic coupled to the comparator, the control logic:
during a sampling phase, powering off the comparator and coupling the sampling capacitor to an input voltage;
during a hold phase that begins subsequent to the sampling phase, de-coupling the sampling capacitor from the input voltage with the comparator powered off;
during a pre-distortion phase subsequent to the hold phase and before a bit cycling phase, powering on the comparator with the sampling capacitor de-coupled from the input voltage,
such that distortion caused by input capacitance variations of the comparator is reduced; and
during the bit-cycling phase subsequent to the pre-distortion phase, coupling the sampling capacitor to a reference voltage with the comparator powered on.
3. A method of converting an analog signal to a digital signal using successive approximation, the method comprising:
after a sampling phase and a hold phase, and before beginning a bit cycling phase, performing pre-distortion of a held signal by performing charge sharing between a sampling capacitor and a parasitic capacitance of a comparator, the held signal sampled during the sampling phase and held during the hold phase;
whereby distortion caused by input capacitance variations of the comparator is reduced in the bit cycling phase in accordance with the pre-distortion.
4. An analog to digital converter for converting an analog signal to a digital signal using successive approximation, comprising:
a sampling unit for sampling an analog input signal to produce a sampled signal;
a capacitor array coupled to the sampling unit for producing an approximation signal;
a comparator coupled to the capacitor array for comparing the approximation signal to the sampled signal; and
a successive approximation register and control logic coupled to the comparator, the control logic:
after a sampling phase and a hold phase, and before beginning a bit cycling phase, performing pre-distortion of a held signal by performing charge sharing between a sampling capacitor and a parasitic capacitance of the comparator, the held signal sampled during the sampling phase and held during the hold phase;
whereby distortion caused by input capacitance variations of the comparator is reduced in the bit cycling phase in accordance with the pre-distortion.
5. A method of converting an analog signal to a digital signal using a main digital-to-analog converter (MDAC) comprising a sampling capacitor and a comparator, the method comprising:
sampling an analog input signal to produce a sampled signal on the sampling capacitor by coupling the sampling capacitor with an input signal while a comparator is powered off;
holding the sampled signal on the sampling capacitor subsequent to the sampling by de-coupling the sampling capacitor from an input signal while the comparator is powered off;
pre-distorting the sampled signal subsequent to the holding by powering on the comparator while holding the sampled signal on the sampling capacitor; and
generating an approximation signal by bit-cycling and in accordance with the pre-distorting.
6. A successive approximation analog-to-digital converter comprising:
a main digital-to-analog converter (MDAC) comprising a sampling capacitor and a comparator; and
control logic coupled with the MDAC to:
sample an analog input signal to produce a sampled signal on the sampling capacitor by coupling the sampling capacitor with an input signal while the comparator is powered off;
hold the sampled signal on the sampling capacitor subsequent to the sampling by de-coupling the sampling capacitor from an input signal while the comparator is powered off;
pre-distort the sampled signal subsequent to the holding by powering on the comparator while holding the sampled signal on the sampling capacitor; and
generating an approximation signal by bit-cycling and in accordance with the pre-distorting.