Substrate materials for quantum processors
In a general aspect, an integrated microwave circuit is disclosed for processing quantum information. The integrated microwave circuit includes a substrate having a first surface and a second surface opposite the first surface. The substrate is formed of a silicon oxide material having a loss tangent no greater than 1×10 −5 at cryogenic temperatures at or below 120 K. The integrated microwave circuit also includes qubit circuitry disposed on the first surface that includes a Josephson junction. A ground plane is disposed on the first surface or the second surface. In some variations, the silicon oxide material is fused silica. In other variations, the silicon oxide material is crystalline quartz.
1. An integrated microwave circuit for processing quantum information, the integrated microwave circuit comprising:
a substrate having a first surface and a second surface opposite the first surface, the substrate formed of a silicon oxide material having a loss tangent no greater than 1×10 −5 at cryogenic temperatures at or below 120 K;
qubit circuitry disposed on the first surface and comprising a Josephson junction; and
a ground plane disposed on the first surface or the second surface.
2. The integrated microwave circuit of claim 1 , wherein the silicon oxide material is fused silica.
3. The integrated microwave circuit of claim 1 , wherein the silicon oxide material is crystalline quartz.
4. The integrated microwave circuit of claim 1 , wherein the silicon oxide material has a dielectric constant less than 13 at cryogenic temperatures at or below 120 K.
5. The integrated microwave circuit of claim 1 , wherein the silicon oxide material has a resistivity of at least 1×10 18 Ω·cm at cryogenic temperatures at or below 120 K.
6. The integrated microwave circuit of claim 1 , wherein the substrate has a thickness ranging from at least 20 μm to no more than 740 μm.
7. The integrated microwave circuit of claim 1 , comprising:
a qubit device disposed on the first surface;
a resonator device disposed on the first surface; and
wherein the qubit device is electromagnetically-coupled to the resonator device.
8. The integrated microwave circuit of claim 7 , wherein the qubit device is capacitively-coupled to the resonator device.
9. The integrated microwave circuit of claim 7 , wherein the qubit device is conductively-coupled to the resonator device.
10. The integrated microwave circuit of claim 1 , wherein the substrate comprises:
a via extending through the substrate from the first surface to the second surface;
an electrically-conducting material disposed within the via and extending from the first surface to the second surface; and
wherein the integrated microwave circuit comprises an electrical pathway between the first and second surfaces, a portion of which, is defined by the electrically-conducting material.
11. The integrated microwave circuit of claim 10 , wherein the electrically-conducting material is a superconducting material.
12. The integrated microwave circuit of claim 10 , wherein the ground plane is disposed on the second surface and electrically-coupled to the electrically-conducting material.
13. The integrated microwave circuit of claim 1 , comprising:
a cap wafer having a mating surface and comprising:
a recess disposed within the cap wafer along the mating surface and configured to enclose a portion of the qubit circuitry when the mating surface is coupled to the first surface of the substrate, and
an electrically-conducting layer disposed over at least a portion of an interior surface of the recess.
14. The integrated microwave circuit of claim 13 , wherein the cap wafer is formed of a silicon oxide material.
15. The integrated microwave circuit of claim 13 , wherein the electrically-conducting layer is formed of a superconducting material.
16. The integrated microwave circuit of claim 13 , wherein the electrically-conducting layer is disposed over the mating surface of the cap wafer.
17. The integrated microwave circuit of claim 1 , comprising:
a resonator device disposed on the second surface;
wherein the substrate comprises:
a via extending through the substrate from the first surface to the second surface, and
an electrically-conducting material disposed within the via and extending from the first surface to the second surface; and
wherein the quantum circuit comprises an electrical pathway between the qubit circuitry and the resonator device, a portion of which, is defined by the electrically-conducting material.
18. The integrated microwave circuit of claim 17 , wherein the electrically-conducting material is a superconducting material.
19. The integrated microwave circuit of claim 17 , comprising a qubit device disposed on the first surface and electromagnetically-coupled to the resonator device on the second surface.
20. The integrated microwave circuit of claim 1 , wherein the substrate comprises:
a recess disposed within the substrate along the second surface and comprising an interior surface; and
an electrically-conducting layer disposed over at least a portion of the interior surface.
21. The integrated microwave circuit of claim 20 , wherein the electrically-conducting layer is formed of a superconducting material.
22. The integrated microwave circuit of claim 20 ,
wherein the electrically-conducting layer is disposed over the second surface;
wherein the substrate comprises:
a via extending through the substrate from the first surface to the second surface, and
an electrically-conducting material disposed within the via and extending from the electrically-conducting layer to the first surface; and
wherein the integrated microwave circuit comprises an electrical pathway between the qubit circuitry and the electrically-conducting layer, a portion of which, is defined by the electrically-conducting material.
23. The integrated microwave circuit of claim 22 , wherein the electrically-conducting layer is formed of a superconducting material.
24. The integrated microwave circuit of claim 22 , wherein the electrically-conducting material is a superconducting material.
25. The integrated microwave circuit of claim 22 , wherein the ground plane comprises the electrically-conducting layer.
26. An integrated circuit system, comprising:
a first substrate, comprising:
a first surface and a second surface opposite the first surface,
qubit circuitry disposed along the first surface and comprising a Josephson junction,
a first ground plane disposed along the second surface, and
a first plurality of vias disposed through the first substrate and electrically-coupling the qubit circuitry to the first ground plane;
a second substrate, comprising:
a third surface and a fourth surface opposite the third surface, the third surface oriented to face the first surface of the first substrate,
microwave-sensing circuitry disposed along the third surface and comprising a resonator device,
a second ground plane disposed along the fourth surface, and
a second plurality of vias disposed through the second substrate and electrically-coupling the microwave-sensing circuitry to the second ground plane;
a first plurality of interconnects coupling the first surface to third surface and defining an electrical pathway between the qubit circuitry of the first substrate and the microwave-sensing circuitry of the second substrate; and
wherein at least one of the first substrate or the second substrate are formed of a silicon oxide material having a loss tangent no greater than 1×10 −5 at cryogenic temperatures at or below 120 K.
27. The integrated circuit system of claim 26 , wherein the silicon oxide material is fused silica.
28. The integrated circuit system of claim 26 , wherein the silicon oxide material is crystalline quartz.
29. The integrated circuit system of claim 26 , wherein the silicon oxide material has a dielectric constant less than 13 at cryogenic temperatures at or below 120 K.
30. The integrated circuit system of claim 26 , wherein the silicon oxide material has a resistivity of at least 1×10 18 Ω·cm at cryogenic temperatures at or below 120 K.
31. The integrated circuit system of claim 26 , wherein the substrate has a thickness ranging from at least 20 μm to no more than 740 μm.
32. The integrated circuit system of claim 26 , comprising:
a second plurality of interconnects coupled to the fourth surface and electrically-coupled to one or both of the second ground plane and the second plurality of vias.
33. The integrated circuit system of claim 26 ,
a second plurality of interconnects coupled to the fourth surface and electrically-coupled to one or both of the second ground plane and the second plurality of vias;
wherein the first substrate, the second substrate, the first plurality of interconnects, and the second plurality of interconnects define a stacked unit in a plurality of stacked units; and
wherein the second plurality of interconnects couples the fourth surface to the second surface between adjacent stacked units.
34. The integrated circuit system of claim 33 , wherein the second plurality of interconnects is electrically-coupled to the second ground plane of the second substrate.