According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.
1. A memory system comprising:
a nonvolatile memory having quad-level cells (QLCs) capable of being used in a single-level cell (SLC) mode; and
a controller electrically connected to the nonvolatile memory, the controller configured to:
select a write mode from an SLC mode and a QLC mode; and
write data into the nonvolatile memory in the selected write mode, wherein
the controller is configured to select the SLC mode to write data received from a host and, based on a utilization value of the memory system, the controller is configured to select the QLC mode to rewrite the data stored in the nonvolatile memory, and
the utilization value is based on a ratio of a total number of mapped logical addresses to an entire logical address space of the memory system.
2. The memory system of claim 1 , wherein the number of logical addresses capable of being mapped is smaller than the number of logical addresses in the entire logical address space of the memory system.
3. The memory system of claim 1 , wherein the utilization value decreases in response to execution of an unmap command.
4. The memory system of claim 1 , wherein when the utilization value reaches a threshold value, the controller is configured to switch the write mode from the SLC write mode to the QLC write mode to write the data received from the host.
5. The memory system of claim 1 , wherein the controller is configured to select the either the SLC or QLC write mode to rewrite the data stored in the nonvolatile memory.
6. The memory system of claim 1 , wherein the controller is configured to check the utilization value periodically and adjust the write mode based upon a result of the check.
7. The memory system of claim 1 , wherein the controller is configured to rewrite LUT (look up table) data stored in the nonvolatile memory by a same write mode as the write mode used to rewrite the data into the nonvolatile memory.
8. A memory system comprising:
a nonvolatile memory having quad-level cells (QLCs) capable of being used in a single-level cell (SLC) mode; and
a controller configured to write data from a host into an SLC area and, based on a utilization value, rewrite the stored data into a QLC area of the nonvolatile memory, wherein
the utilization value is determined as a ratio of logical addresses mapped to a physical address space of the nonvolatile memory.
9. The memory system of claim 8 , wherein the utilization value decreases in response to execution of an unmap command.
10. The memory system of claim 8 , wherein when the utilization value reaches a threshold value, the controller is configured to write the data from the host in the QLC area.
11. The memory system of claim 8 , wherein the controller is configured to rewrite the data stored in the nonvolatile memory using either the SLC mode or a QLC mode.
12. The memory system of claim 8 , wherein the controller is configured to check the utilization value periodically and adjust a write mode based upon a result of the check.
13. The memory system of claim 8 , wherein the controller is configured to rewrite LUT (look up table) data stored in the nonvolatile memory by a same write mode as the write mode used to rewrite the data into the nonvolatile memory.