IP Library Granted Patent US 11,335,788
Granted Patent B2
US 11,335,788 · App. 16/118,064 · Granted May 17, 2022

Semiconductor devices, transistors, and related methods for contacting metal oxide semiconductor devices

Inventors: Durai Vishak Nirmal Ramaswamy (Boise, ID); Ramanathan Gandhi (Boise, ID); Scott E. Sills (Boise, ID)
Assignee: Micron Technology, Inc.
H01L29/45H01L29/42356H01L29/66969H01L29/7869H01L29/78642H01L29/78693H01L27/10805H01L27/10873H01L29/7827
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Quick Facts
Patent No.
US 11,335,788
App. No.
16/118,064
Granted
May 17, 2022
Kind
B2
Abstract

A semiconductor device is disclosed. The semiconductor device includes a transistor including a source contact, a drain contact, and a channel region including an oxide semiconductor material as the channel material. At least one of the drain contact or the source contact includes a conductive material, such as ruthenium, to reduce the Schottky effects at the interface with the channel material.

Claims (46)

1. A semiconductor device, comprising:

a first conductive line structure;

a second conductive line structure overlying the first conductive line structure;

a transistor between the first conductive line structure and the second conductive line structure, the transistor comprising:

at least one gate electrode;

a channel comprising an oxide semiconductor material; and

a source contact structure in physical contact with the oxide semiconductor material of the channel and the first conductive line structure, the source contact structure continuously extending across an entirety of an upper surface of the first conductive line structure and comprising:

a first region at an interface with the oxide semiconductor material and comprising ruthenium oxide; and

a second region directly between the first region and the upper surface of the first conductive line structure and comprising elemental ruthenium;

a drain contact structure in physical contact with the oxide semiconductor material of the channel and a lower surface of the second conductive line structure; and

a gate insulator material directly on an upper, horizontally extending surface of the source contact structure, the gate insulator material directly physically contacting and horizontally extending between the oxide semiconductor material of the channel and the at least one gate electrode.

2. The semiconductor device of claim 1 , wherein the oxide semiconductor material is selected from the group consisting of ZTO, IZO, IGZO, In 2 O 3 , SnO 2 , and InGaSiO.

3. The semiconductor device of claim 1 , wherein:

the source contact structure has a different material composition than the first conductive line structure; and

the drain contact structure has a different material composition than the second conductive line structure.

4. The semiconductor device of claim 1 , wherein the transistor is configured in a vertical orientation.

5. The semiconductor device of claim 1 , wherein the transistor is configured in a planar orientation.

6. The semiconductor device of claim 1 , further comprising a memory cell including a storage element operably coupled with the transistor.

7. The semiconductor device of claim 1 , wherein the source contact structure is substantially planar.

8. The semiconductor device of claim 1 , further comprising a gate insulator material extending from a side surface of the at least one gate electrode to a side surface of the oxide semiconductor material of the channel.

9. A semiconductor device, comprising:

a transistor comprising:

at least one gate electrode;

a channel comprising an oxide semiconductor material; and

a drain contact structure vertically overlying and physically contacting the channel, the drain contact structure comprising indium tin oxide (ITO);

a source contact structure vertically underlying and physically contacting the channel, the source contact structure comprising additional ITO;

at least one conductive gate structure horizontally neighboring the channel and substantially confined within vertical boundaries of the channel, the conductive gate structure having a side surface substantially coplanar with a side surface of the source contact structure; and

a gate insulator material directly on an upper, horizontally extending surface of the source contact structure, the gate insulator material directly physically contacting and horizontally extending between the oxide semiconductor material of the channel and the at least one conductive gate structure;

a first conductive line structure vertically underlying and in direct physical contact with the source contact structure, the first conductive line structure having a different material composition than the source contact structure; and

a second conductive line structure vertically overlying and in direct physical contact with the drain contact structure, the second conductive line structure having a different material composition than the drain contact structure.

10. The semiconductor device of claim 9 , wherein the at least one gate electrode comprises only one gate electrode.

11. The semiconductor device of claim 9 , wherein the at least one gate electrode comprises two gate electrodes.

12. The semiconductor device of claim 9 , wherein the channel consists of an amorphous oxide semiconductor material.

13. The semiconductor device of claim 9 , further comprising a storage element operably coupled with the transistor, the transistor comprises an access device transistor for the storage element.

14. The semiconductor device of claim 9 , wherein the transistor is a select device for a memory component selected from the group consisting of a deck of memory cells and a back end of line routing component.

15. The semiconductor device of claim 9 , wherein the source contact structure is embedded within the first conductive line structure.

16. The semiconductor device of claim 9 , wherein the source contact structure is coextensive with the first conductive line structure.

17. A method of forming a transistor, comprising:

forming a conductive gate structure in dielectric material overlying a first conductive line structure;

forming a trench in the dielectric material, the trench exposing a side surface of the conductive gate structure and an upper surface of the first conductive line structure;

forming a source contact structure comprising one or more of ruthenium and indium tin oxide (ITO) within the trench and on the first conductive line structure, the source contact structure having a different material composition than the first conductive line structure;

forming a channel comprising an oxide semiconductor material within the trench and on the source contact structure, an interface between the source contact structure and the channel comprising a non-Schottky interface; and

forming a drain contact structure on the channel.

18. The method of claim 17 , wherein the source contract structure and the drain contact structure have substantially the same material composition.

19. The method of claim 17 , further comprising forming a second conductive line structure on the drain contact structure, the second conductive line structure horizontally extending orthogonal to the first conductive line structure and having a different material composition than the drain contact structure.

20. The method of claim 17 , wherein the oxide semiconductor material is selected from the group consisting of ZTO, IZO, IGZO, In 2 O 3 , SnO 2 , and InGaSiO.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051028/0835 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050719/0550 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.., AS COLLATERAL AGENT
Reel/Frame 047630/0756 →
SUPPLEMENT NO. 10 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048102/0420 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2018
From: RAMASWAMY, DURAI VISHAK NIRMAL; GANDHI, RAMANATHAN; SILLS, SCOTT E.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047355/0150 →