Hardware sort accelerator sharing first level processor cache

1. A computer processor comprising:

a memory unit configured to store key values to be loaded into a partial tournament sort;

a processor cache configured to obtain data from the memory unit indicating the key values;

a hardware merge sort accelerator in signal communication with the memory unit and the processor cache, the merge sort accelerator configured to generate a tournament tree based on the key values and perform a partial tournament sort on a digit by digit basis to store a first portion of tournament results in the processor cache while excluding a second portion of the tournament results from the processor cache.

2. The computer processor of claim 1 , wherein the key value represents a numeral including a plurality of digits.

3. The computer processor of claim 2 , wherein the merge sort accelerator performs the partial tournament sort by performing a first tournament to determine a first digit of an overall winning key value, and performing a second tournament to determine a second digit of the overall winning key value.

4. The computer processor of claim 3 , wherein the merge sort accelerator determines the first portion of the tournament results based on a winning digit of a particular match between a first digit of a first key value and a first digit of a second key value different from the first key value.

5. The computer processor of claim 4 , wherein the merge sort accelerator determines the winning digit as a lowest value among a comparison between digits of the first and second keys of a given match.

6. The computer processor of claim 4 , wherein the merge sort accelerator determines the overall winning key value of the partial tournament sort by selecting a key value from the tournament list and performing a plurality of passes through the tournament tree using the selected key value.

7. The computer processor of claim 6 , wherein the overall winning key value is stored from the merge sort accelerator to the memory unit.

8. The computer processor of claim 7 , wherein each overall winning key value that is stored to the memory unit is automatically stored sequentially with respect to one another.

9. A computer-implemented method of sorting a plurality of data values stored in a hardware computer processor, the method comprising:

storing, in a memory unit of the computer processor, key values to be loaded into a partial tournament sort;

obtaining, via a processor cache, tree data from the memory unit indicating the key values;

generating, via a hardware merge sort accelerator, a tournament tree based on the key values; and

performing, via the merge sort accelerator, a partial tournament sort on a digit by digit basis to store a first portion of tournament results in the processor cache while excluding a second portion of the tournament results from the processor cache.

10. The method of claim 9 , wherein the key value represents a numeral including a plurality of digits.

11. The method of claim 10 , wherein performing the partial tournament sort comprises:

performing a first tournament to determine a first digit of an overall winning key value; and

performing a second tournament to determine a second digit of the overall winning key value.

12. The method of claim 11 , wherein determining the first portion of the tournament results is based on a winning digit of a particular match between a first key value and a second key value different from the first key value, the winning digit determined according to a comparison between a first digit of the first key value and a first digit of the second key value.

13. The method of claim 12 , wherein the winning digit is determined as a lowest value among a comparison between digits of the first and second keys of a given match.

14. The method of claim 12 , further comprising:

determining the overall winning key value of the partial tournament sort by selecting a key value from a tournament list; and

performing a plurality of passes through the tournament tree using the selected key value.

15. The method of claim 14 , further comprising storing the overall winning key value from the merge sort accelerator to the memory unit.

16. The method of claim 15 , further comprising updating the memory unit in response to storing each overall winning key value to the memory unit such that each overall winning key value is automatically stored sequentially with respect to one another.

17. A computer program product to control an electronic computer processor to sort data, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by the electronic computer processor to perform operations comprising:

storing, in a memory unit of the computer processor, key values to be loaded into a partial tournament sort;

obtaining, via a processor cache, tree data from the memory unit indicating the key values;

generating, via a hardware merge sort accelerator, a tournament tree based on the key values; and

performing, via the merge sort accelerator, a partial tournament sort on a digit by digit basis to store a first portion of tournament results in the processor cache while excluding a second portion of the tournament results from the processor cache,

wherein the key value represents a numeral including a plurality of digits.

18. The computer program product of claim 17 , wherein performing the partial tournament sort comprises:

performing a first tournament to determine a first digit of an overall winning key value;

performing a second tournament to determine a second digit of the overall winning key value; and

determining the first portion of the tournament results is based on a winning digit of a particular match between a first key value and a second key value different from the first key value,

wherein the winning digit is determined according to a comparison between a first digit of the first key value and a first digit of the second key value.

19. The computer program product of claim 18 , further comprising:

determining an overall winning key value of the partial tournament sort by selecting a key value from a tournament list; and

performing a plurality of tournament passes through the tournament tree using the selected key value,

wherein a first digit of the overall winning key value is determined in response to completing a first tournament pass; and

wherein a second digit of the overall winning key value is determined in response to completing a second tournament pass.

20. The computer program product of claim 19 , further comprising:

storing the overall winning key value from the merge sort accelerator to the memory unit; and

updating the memory unit in response to storing each overall winning key value to the memory unit such that each overall winning key value is automatically stored sequentially with respect to one another.