Methods of operating voltage generation circuits

1. A method of operating a voltage generation circuit, comprising:

applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit;

when the clock signal has a particular logic level, and a voltage level of an output of the voltage driver is less than a threshold, connecting the output of the voltage driver to a first voltage node configured to receive a first voltage and isolating the output of the voltage driver from a second voltage node configured to receive a second voltage, greater than the first voltage;

when the clock signal has the particular logic level, and the voltage level of the output of the voltage driver is greater than the threshold, connecting the output of the voltage driver to the second voltage node and isolating the output of the voltage driver from the first voltage node; and

when the clock signal has a different logic level, connecting the output of the voltage driver to a third voltage node configured to receive a third voltage, less than the first voltage.

2. The method of claim 1 , further comprising:

when the clock signal has the particular logic level, and the voltage level of the output of the voltage driver is equal to the threshold, connecting the output of the voltage driver to the second voltage node.

3. The method of claim 1 , wherein applying the clock signal to the input of the voltage driver of the stage of the voltage generation circuit comprises applying the clock signal to the input of the voltage driver of the stage of a charge pump.

4. The method of claim 1 , wherein applying the clock signal to the input of the voltage driver of the stage of the voltage generation circuit comprises applying the clock signal to an input of a respective voltage driver of each stage of a first plurality of stages of the voltage generation circuit.

5. The method of claim 4 , wherein the clock signal is a first clock signal, the method further comprising:

applying a second clock signal to an input of a respective voltage driver of each stage of a second plurality of stages of the voltage generation circuit;

wherein the second clock signal has a same frequency as the first clock signal; and

wherein a phase of the second clock signal is different than a phase of the first clock signal.

6. The method of claim 5 , wherein applying the second clock signal to the input of a respective voltage driver of each stage of the second plurality of stages of the voltage generation circuit comprises applying the second clock signal having a phase that is opposite the phase of the first clock signal.

7. The method of claim 1 , wherein connecting the output of the voltage driver to the first voltage node when the clock signal has the particular logic level and the voltage level of the output of the voltage driver is less than the threshold comprises connecting the output of the voltage driver to the first voltage node when the clock signal has the particular logic level and the voltage level of the output of the voltage driver is less than a threshold having a voltage level less than a voltage level of the first voltage and greater than a voltage level of the third voltage.

8. The method of claim 1 , wherein connecting the output of the voltage driver to the second voltage node configured to receive the second voltage comprises connecting the output of the voltage driver to the second voltage node configured to receive an output voltage of a different voltage generation circuit.

9. The method of claim 1 , further comprising generating a voltage selected from a group consisting of an increasing voltage and a decreasing voltage at an output of the voltage generation circuit.

10. A method of operating a voltage generation circuit, comprising:

applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit;

when the clock signal has a particular logic level, and a voltage level of an output of the voltage driver is less than a threshold, connecting the output of the voltage driver to a first voltage node configured to receive a first voltage and isolating the output of the voltage driver from a second voltage node configured to receive a second voltage, greater than the first voltage;

when the clock signal has the particular logic level, and the voltage level of the output of the voltage driver is greater than or equal to the threshold, connecting the output of the voltage driver to the second voltage node and isolating the output of the voltage driver from the first voltage node; and

when the clock signal has a different logic level, opposite of the particular logic level, connecting the output of the voltage driver to a third voltage node configured to receive a third voltage, less than the first voltage.

11. The method of claim 10 , wherein applying the clock signal to the input of the voltage driver of the stage of the voltage generation circuit comprises applying the clock signal to the input of the voltage driver of the stage of a charge pump.

12. The method of claim 10 , wherein applying the clock signal to the input of the voltage driver of the stage of the voltage generation circuit comprises applying the clock signal to an input of a respective voltage driver of each stage of a first plurality of stages of the voltage generation circuit.

13. The method of claim 12 , wherein the clock signal is a first clock signal, the method further comprising:

applying a second clock signal to an input of a respective voltage driver of each stage of a second plurality of stages of the voltage generation circuit mutually exclusive from the first plurality of stages of the voltage generation circuit;

wherein the second clock signal has a same frequency as the first clock signal; and

wherein the second clock signal has a phase opposite a phase of the first clock signal.

14. The method of claim 13 , wherein applying the second clock signal to the input of the respective voltage driver of each stage of the second plurality of stages of the voltage generation circuit comprises applying the second clock signal to the input of the respective voltage driver of a particular stage of the second plurality of stages of the voltage generation circuit that is immediately adjacent two stages of the first plurality of stages of the voltage generation circuit and connected in series with those two stages of the first plurality of stages of the voltage generation circuit.

15. The method of claim 10 , wherein connecting the output of the voltage driver to the first voltage node when the clock signal has the particular logic level and the voltage level of the output of the voltage driver is less than the threshold comprises connecting the output of the voltage driver to the first voltage node when the clock signal has the particular logic level and the voltage level of the output of the voltage driver is less than a threshold having a voltage level less than a voltage level of the first voltage and greater than a voltage level of the third voltage.

16. The method of claim 10 , wherein connecting the output of the voltage driver to the second voltage node configured to receive the second voltage comprises connecting the output of the voltage driver to the second voltage node configured to receive an output voltage of a different voltage generation circuit.

17. The method of claim 10 , further comprising generating a voltage selected from a group consisting of an increasing voltage and a decreasing voltage at an output of the voltage generation circuit.

18. A method of operating a voltage generation circuit, comprising:

applying a first clock signal to an input of a voltage driver of a first stage of a plurality of stages of the voltage generation circuit;

applying a second clock signal to an input of a voltage driver of a second stage of the plurality of stages of the voltage generation circuit, wherein the second clock signal has a same frequency as the first clock signal and a phase opposite of a phase of the first clock signal;

when the first clock signal has a particular logic level, and a voltage level of an output of the voltage driver of the first stage is less than a threshold, connecting the output of the voltage driver of the first stage to a first voltage node configured to receive a first voltage;

when the first clock signal has the particular logic level, and the voltage level of the output of the voltage driver of the first stage is greater than or equal to the threshold, connecting the output of the voltage driver of the first stage to a second voltage node configured to receive a second voltage, greater than the first voltage;

when the first clock signal has a different logic level, opposite of the particular logic level, connecting the output of the voltage driver of the first stage to a third voltage node configured to receive a third voltage, less than the first voltage;

when the second clock signal has the particular logic level, and a voltage level of an output of the voltage driver of the second stage is less than the threshold, connecting the output of the voltage driver of the second stage to the first voltage node;

when the second clock signal has the particular logic level, and the voltage level of the output of the voltage driver of the second stage is greater than or equal to the threshold, connecting the output of the voltage driver of the second stage to the second voltage node; and

when the second clock signal has the different logic level, connecting the output of the voltage driver of the second stage to the third voltage node.

19. The method of claim 18 , connecting the output of the voltage driver of the first stage to the second voltage node when the first clock signal has the particular logic level and the voltage level of the output of the voltage driver of the first stage is greater than or equal to the threshold comprises a threshold that has a higher voltage level than the third voltage and a lower voltage level than the first voltage.

20. The method of claim 18 , further comprising:

passing a voltage level of the first stage to the second stage when the first clock signal has the particular logic level and the second clock signal has the different logic level.