DRAM sense amplifier active matching fill features for gap equivalence systems and methods
View Patent ↗A memory device may include a memory array with multiple memory cells and one or more sense amplifiers connected to the memory array. Each sense amplifier may include a matched pair of transistors. An active matching fill feature may also be included proximate to at least one transistor of the matched pair of transistors.
1. A memory device comprising:
a memory array comprising a plurality of memory cells;
one or more sense amplifiers coupled to the memory array and each comprising a matched pair of transistors; and
an active matching fill feature proximate to at least one transistor of the matched pair of transistors, wherein the active matching fill feature shortens a gap between a first active material of the at least one transistor of the matched pair of transistors and a second active material of a component of the memory device.
2. The memory device of claim 1 , wherein a first active material of a first transistor of the matched pair of transistors comprises a first distance to a second active material of a component of the memory device.
3. The memory device of claim 2 , wherein a third active material of a second transistor of the matched pair of transistors comprises a second distance to a fourth active material of the active matching fill feature, wherein the second distance is approximately equal to the first distance.
4. The memory device of claim 1 , wherein the active matching fill feature is an n-type active material.
5. The memory device of claim 1 , wherein the active matching fill feature is introduced into a read/write section of the memory device.
6. The memory device of claim 1 , wherein the one or more sense amplifier comprises a voltage transfer characteristic (VTC) sense amplifier.
7. The memory device of claim 1 , wherein the memory device comprises a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM).
8. A memory device comprising:
a memory array comprising a plurality of memory cells;
one or more sense amplifiers coupled to the memory array and each comprising a matched pair of transistors; and
an active matching fill feature proximate to at least one transistor of the matched pair of transistors, wherein the active matching fill feature is separated from the at least one transistor of the matched pair of transistors via shallow trench isolation (STI).
9. The memory device of claim 1 , wherein a sense amplifier of the one or more sense amplifiers is configured to output a logical state value based at least in part on a voltage of a memory cell of the plurality of memory cells and a threshold voltage.
10. The memory device of claim 9 , wherein the active matching fill feature is configured to reduce a variation in the threshold voltage of a first transistor of the matched pair of transistors and the threshold voltage of a second transistor of the matched pair of transistors.
11. A system comprising:
a controller; and
a memory device communicatively coupled to the controller, wherein the memory device comprises:
a plurality of memory cells;
a sense amplifier comprising:
a first transistor comprising a first active area of active material; and
a second transistor comprising a second active area of the active material, wherein the sense amplifier is configured to read and output a logic level based at least in part on a voltage of one of the plurality of memory cells; and
an active matching fill feature configured to balance distances between active areas of the first active area, the second active area, and surrounding active areas.
12. The system of claim 11 , wherein the active material is a p-type material, and the active matching fill feature comprises an n-type material.
13. The system of claim 11 , wherein the active matching fill feature comprises a doped semiconductor on a substrate of the memory device.
14. The system of claim 11 , wherein the controller is configured to select which of the plurality of memory cells the sense amplifier is configured to read.
15. The system of claim 11 , wherein the active matching fill feature comprises a capacitor or transistor in an open circuit of the memory device.
16. A method, comprising:
layering active material on a substrate to form at least two transistors of a memory device, wherein the at least two transistors are matched to have substantially similar activation parameters; and
layering an active matching fill feature proximate to a first transistor of the at least two transistors to create a first gap between a first active area of the first transistor and a second active area of the active matching fill feature, wherein the first gap is approximately equal to a second gap between a second transistor of the at least two transistors and a third active area of the memory device.
17. The method of claim 16 , wherein layering an active matching fill feature comprises determining a size of the second gap and layering the active matching fill feature at a location on the memory device to make the first gap approximately equal to the size of the second gap.
18. The method of claim 16 , wherein the memory device comprises a sense amplifier, wherein the sense amplifier comprises the at least two transistors.
19. The method of claim 16 , comprising layering non-conductive or semi-conductive material around the active matching fill feature, wherein the non-conductive or semi-conductive material is configured to reduce stray capacitance.