IP Library Granted Patent US 11,056,351
Granted Patent B2
US 11,056,351 · App. 16/119,543 · Granted Jul 6, 2021

Process monitor for wafer thinning

Inventor: Stephen L. Morein (San Jose, CA)
Assignee: SYNAPTICS INCORPORATED
H01L21/3212B24B49/10H01L21/683H01L22/12H01L22/14
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Quick Facts
Patent No.
US 11,056,351
App. No.
16/119,543
Granted
Jul 6, 2021
Kind
B2
Abstract

A system and method for thinning an integrated circuit (IC) wafer. The system includes a support structure to hold the IC wafer and a mechanism to operate on the IC wafer. The support structure includes one or more inductive coils configured to transmit a power signal to the IC wafer and receive a feedback signal from the IC wafer. The system further includes a process controller to control the operation based at least in part on the feedback signal received from the IC wafer.

Claims (29)

1. A method of operating on an integrated circuit (IC) wafer, comprising:

transmitting a power signal inductively to the IC wafer, the power signal powering wafer measurement circuitry disposed in the IC wafer;

receiving a feedback signal inductively from the wafer measurement circuitry on the IC wafer;

monitoring a characteristic of the received feedback signal; and

removing layers of material from a surface of the IC wafer until the monitored characteristic reaches a threshold level.

2. The method of claim 1 , wherein the layers of material are removed using backgrinding or chemical mechanical polishing (CMP) techniques.

3. The method of claim 1 , wherein the feedback signal is generated by a resistance-capacitance (RC) oscillator, provided on the IC wafer, in response to the power signal and the monitored characteristic is a frequency of the feedback signal, and wherein the removing comprises:

ceasing the removal of layers of the IC wafer when the monitored frequency reaches a threshold frequency.

4. The method of claim 1 , wherein the removing comprises:

determining a resistance of the material based at least in part on the monitored characteristic; and

ceasing the removal of layers of the IC wafer when the resistance of the material reaches a threshold resistance.

5. The method of claim 1 , wherein the characteristic indicates a thickness of the material, and wherein the removing comprises:

determining a thickness of the IC wafer based at least in part on the monitored characteristic; and

ceasing the removal of layers of the IC wafer when the thickness of the IC wafer reaches a threshold thickness.

6. A method of operating on an integrated circuit (IC) wafer, comprising:

transmitting a plurality of power signals inductively to the IC wafer, the plurality of power signals powering a plurality of wafer measurement circuits disposed in the IC wafer, wherein each of the power signals is transmitted to a different region of the IC wafer;

receiving a respective feedback signal inductively from each of the wafer measurement circuits on the IC wafer;

monitoring a characteristic of each of the received feedback signals; and

removing layers of material from a surface of the IC wafer until the monitored characteristic for at least one of the received feedback signals reaches a threshold level.

7. The method of claim 6 , wherein the removing comprises:

determining, for each of the received feedback signals, a resistance of the material in a corresponding region of the IC wafer based at least in part on the monitored characteristic; and

ceasing the removal of layers of the IC wafer when the resistance of the material reaches a threshold resistance in at least one of the regions of the IC wafer.

8. The method of claim 7 , wherein the ceasing comprises:

ceasing the removal of layers of the IC wafer only when the resistance of the material reaches the threshold resistance in each of the regions of the IC wafer.

9. The method of claim 6 , wherein the removing comprises:

determining, for each of the received feedback signals, a thickness of the IC wafer in a corresponding region based at least in part on the monitored characteristic; and

ceasing the removal of layers of the IC wafer when the thickness of the IC wafer reaches a threshold thickness in at least one of the regions.

10. The method of claim 9 , wherein the ceasing comprises:

ceasing the removal of layers of the IC wafer only when the thickness of the IC wafer reaches the threshold thickness in each of the regions.

Assignments (2)
SECURITY INTEREST Recorded Feb 14, 2020
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 051936/0103 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2018
From: MOREIN, STEPHEN L.
To: SYNAPTICS INCORPORATED
Reel/Frame 046769/0715 →