Memory arrays comprising vertically-alternating tiers of insulative material and memory cells and methods of forming a memory array

1. A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising a transistor and a capacitor disposed horizontally relative to each other within the tiers of memory cells, the capacitor comprising:

a first electrode electrically coupled to a source/drain region of the transistor, the first electrode being disposed at an elevation over a substrate equivalent to an elevation over the substrate of a channel region of the transistor, the first electrode comprising an annulus in a straight-line horizontal cross-section;

a capacitor insulator radially inward of the first electrode annulus; and

a second electrode radially inward of the capacitor insulator; and

a capacitor-electrode structure extending elevationally through multiple of the vertically-alternating tiers, individual of the second electrodes of individual capacitors being electrically coupled to the elevationally-extending capacitor-electrode structure; and

a sense line electrically coupled to another source/drain region of multiple transistors that are in different memory-cell tiers.

2. The array of claim 1 wherein the capacitor-electrode structure comprises a pillar.

3. The array of claim 1 wherein the capacitor insulator extends elevationally through the vertically-alternating tiers.

4. The array of claim 1 wherein the capacitor insulator comprises an annulus in a straight-line horizontal cross-section.

5. The array of claim 4 wherein the capacitor insulator extends elevationally through the vertically-alternating tiers.

6. The array of claim 1 wherein the second electrode is not annular in any straight-line horizontal cross-section.

7. The array of claim 1 wherein the capacitor-electrode structure is not annular in any straight-line horizontal cross-section.

8. The array of claim 1 wherein the capacitor-electrode structure extends vertically or within 10° of vertical.

9. The array of claim 1 wherein the sense line comprises a sense-line structure extending elevationally through the vertically-alternating tiers, individual of the second source/drain regions of individual transistors that are in different memory-cell tiers being electrically coupled to the elevationally-extending sense-line structure.

10. The array of claim 9 wherein the sense-line structure comprises a pillar.

11. The array of claim 9 wherein the sense line comprises a horizontal longitudinally-elongated conductive line that is above or below the vertically-alternating tiers and is directly electrically coupled to the sense-line structure.

12. The array of claim 1 wherein the capacitor-electrode structure is directly electrically coupled to a horizontally-elongated capacitor-electrode construction that is above or below the vertically-alternating tiers.

13. The array of claim 1 wherein,

the sense line comprises a sense-line structure extending elevationally through the vertically-alternating tiers, individual of the second source/drain regions of individual transistors being electrically coupled to the elevationally-extending sense-line structure;

the sense line comprises a horizontal longitudinally-elongated conductive line that is above the vertically-alternating tiers and is directly electrically coupled to the sense-line structure; and

the capacitor-electrode structure is directly electrically coupled to a horizontally-elongated capacitor-electrode construction that is above the vertically-alternating tiers and below the horizontal longitudinally-elongated conductive line.

14. A memory array, comprising:

vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:

a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the at least a portion between the first and second source/drain regions; and

a capacitor disposed horizontally relative to the transistor, the capacitor comprising:

a first electrode electrically coupled to the first source/drain region of the transistor, the first electrode being disposed at an elevation over a substrate equivalent to an elevation over the substrate of the channel region and comprising an annulus in a straight-line horizontal cross-section;

a capacitor insulator radially inward of the first electrode annulus; and

a second electrode radially inward of the capacitor insulator;

a capacitor-electrode structure extending elevationally through the vertically-alternating tiers, the second electrode of individual of the capacitors comprising a portion of the elevationally-extending capacitor-electrode structure; and

a sense-line structure extending elevationally through the vertically-alternating tiers, individual of the second source/drain regions of individual transistors that are in different memory-cell tiers being electrically coupled to the elevationally-extending sense-line structure.

15. The array of claim 14 wherein all of the channel region is horizontally-oriented for horizontal current flow there-through.

16. The array of claim 14 wherein the first electrode is directly electrically coupled to the first source/drain region.

17. The array of claim 14 wherein the sense-line structure is directly electrically coupled to a horizontal longitudinally-elongated sense line that is above or below the vertically-alternating tiers.

18. The array of claim 14 wherein the capacitor-electrode structure is directly electrically coupled to a horizontally-elongated capacitor-electrode construction that is above or below the vertically-alternating tiers.