STACKED WAFER INTEGRATED CIRCUIT
A method for manufacturing a stacked wafer integrated circuit (IC) device. The method is performed by fabricating first circuitry on a top surface of a first IC wafer and depositing one or more electrical insulators, between the first circuitry, through a depth of the first IC wafer such that the one or more electrical insulators are not exposed on a bottom surface of the first IC wafer. Layers of semiconductor substrate are subsequently removed from a bottom surface of the first IC wafer until the one or more electrical insulators become exposed on the bottom surface of the first IC wafer.
1 . A method of manufacturing an integrated circuit (IC) device, comprising:
fabricating first circuitry on a top surface of a first IC wafer;
depositing one or more electrical insulators, between the first circuitry, through a depth of the first IC wafer such that the one or more electrical insulators are not exposed on a bottom surface of the first IC wafer; and
removing layers of semiconductor substrate from a bottom surface of the first IC wafer until the one or more electrical insulators become exposed on the bottom surface of the first IC wafer.
2 . The method of claim 1 , wherein the layers of semiconductor substrate are removed using backgrinding or chemical mechanical polishing (CMP) techniques.
3 . The method of claim 1 , wherein one or more circuit components are created on the first IC wafer as a result of removing the layers of semiconductor substrate.
4 . The method of claim 1 , wherein one or more circuit components are electrically isolated on the first IC wafer as a result of removing the layers of semiconductor substrate.
5 . The method of claim 1 , further comprising:
aligning the first IC wafer with a second IC wafer, in a stacked configuration, such that the top surface of the first IC wafer faces a top surface of the second IC wafer; and
bonding the first IC wafer with the second IC wafer in the stacked configuration such that the first circuitry disposed on the top surface of the first IC wafer is electrically coupled to second circuitry disposed on the top surface of the second IC wafer.
6 . The method of claim 5 , wherein, as a result of the bonding, the bottom surface of the first IC wafer forms a top surface of the IC device and the bottom surface of the second IC wafer forms a bottom surface of the IC device.
7 . The method of claim 5 , wherein the first circuitry is formed on the first IC wafer using a first process node, and wherein the second circuitry is formed on the second IC wafer using a second process node that is different than the first process node.
8 . The method of claim 7 , wherein the first process node is smaller than the second process node.
9 . The method of claim 5 , wherein the first circuitry corresponds to digital circuitry and the second circuitry corresponds to analog circuitry.
10 . The method of claim 9 , wherein the digital circuitry is formed on the first IC wafer using a low-power (LP) or embedded-flash (EF) process, and wherein the analog circuitry is formed on the second IC wafer using a high-voltage (HV) process.
11 . The method of claim 2 , wherein the removing comprises:
removing the layers of semiconductor substrate until a combined thickness of the first IC wafer and the second IC wafer, in the stacked configuration, is less than or equal to a threshold thickness.
12 . The method of claim 11 , wherein the threshold thickness corresponds to a thickness of the first IC wafer prior to removing the layers of semiconductor substrate.
13 . An integrated circuit (IC) device, comprising:
a first circuit component disposed in a first region of an IC wafer;
a second circuit component disposed in a second region of the IC wafer; and
an electrical insulator deposited between the first region and the second region, the electrical insulator extending from a top surface of the IC wafer to a bottom surface of the IC wafer and electrically isolating the first circuit component from the second circuit component.
14 . The IC device of claim 13 , wherein at least one of the first or second circuit components comprises a vertical diode having a first terminal provided on the top surface of the IC wafer and a second terminal provided on the bottom surface of the IC wafer.
15 . The IC device of claim 13 , wherein at least one of the first or second circuit components comprises a via having a first terminal provided on the top surface of the IC wafer and a second terminal provided on the bottom surface of the IC wafer.
16 . The IC device of claim 13 , wherein at least one of the first or second circuit components comprises a horizontal diode having first and second terminals provided on the top surface of the IC wafer.
17 . The IC device of claim 13 , wherein at least one of the first or second circuit components comprises a vertical lateral double-diffused metal oxide semiconductor (LDMOS) having a first terminal provided on the top surface of the IC wafer and a second terminal provided on the bottom surface of the IC wafer.
18 . The IC device of claim 13 , wherein at least one of the first or second circuit components comprises Schottky diode having a first terminal provided on the top surface of the IC wafer and a second terminal provided on the bottom surface of the IC wafer.
19 . The IC device of claim 13 , wherein at least one of the first or second circuit components comprises a bipolar junction transistor having a first terminal provided on the top surface of the IC wafer and a second terminal provided on the bottom surface of the IC wafer.
20 . The IC device of claim 13 , wherein the first circuit component comprises a first diode and the second circuit component comprises a second diode, wherein the first diode is coupled in series with the second diode across the top surface or the bottom surface of the IC wafer to form an electrostatic discharge (ESD) diode.