Semiconductor memory device and manufacturing method for same
According to one embodiment, semiconductor memory device includes a first conductive layer, a plurality of second conductive layers stacked over the first conductive layer in a first direction, a memory pillar extending in the plurality of second conductive layers in the first direction, and a first layer extending from the first conductive layer through a portion of the plurality of second conductive layers in the first direction in contact with a the plurality of second conductive layers, the first layer including a first portion having a first cross section in the plane of second and third directions that are perpendicular to each other and to the first direction, and a second portion having a second cross section, different from the first cross section, in the plane of the second and third directions.
1. A semiconductor memory device comprising:
a first conductive layer;
a plurality of second conductive layers stacked above the first conductive layer in a first direction;
a third conductive layer disposed between the first conductive layer and a lowermost layer of the plurality of second conductive layers;
a pillar including a semiconductor layer and a charge storage layer provided between the semiconductor layer and the plurality of second conductive layers, the pillar extending through the plurality of second conductive layers and the third conductive layer in the first direction; and
a slit extending in the first direction and a second direction crossing the first direction, the slit separating the plurality of second conductive layers and the third conductive layer in a third direction crossing the first and second directions, the slit including a first portion penetrating the third conductive layer and being in contact with the first conductive layer and a second portion extending through and being in contact with the plurality of second conductive layers and being in contact with the first portion, wherein
the semiconductor layer of the pillar extends inside the first conductive layer, and a side surface of the semiconductor layer contacts the first conductive layer,
the first portion of the slit has a first width in the third direction at a location facing the third conductive layer,
the second portion of the slit has a second width in the third direction at a location facing a lowermost layer of the plurality of second conductive layers,
the semiconductor layer has a third width in the third direction at a location facing the third conductive layer, and
the first width is greater than the second width and the third width.
2. The semiconductor device according to claim 1 , wherein the second portion of the slit has a greater length in the first direction than a length of the first portion of the slit in the first direction.
3. The semiconductor memory device according to claim 1 , wherein the second portion of the slit contacts the first portion of the slit at a location between the first conductive layer and one of the plurality of second conductive layers that is closest to the first conductive layer.
4. The semiconductor memory device according to claim 1 , wherein
a thickness of the third conductive layer in the first direction is greater than a thickness of at least one of the plurality of second conductive layers in the first direction, and
the semiconductor memory device further comprises a second insulating layer located on the third conductive layer.
5. The semiconductor memory device according to claim 1 , wherein
a thickness of the third conductive layer in the first direction is greater than a thickness of at least one of the plurality of second conductive layers in the first direction,
the semiconductor memory device further comprises a second insulating layer located on the third conductive layer, and
the second portion of the slit contacts the first portion of the slit at a location adjoining the second insulating layer.
6. The semiconductor memory device according to claim 5 , wherein a surface of the first portion of the slit facing the second portion extends along a surface of the third conductive layer facing the second insulating layer.
7. The semiconductor memory device according to claim 1 , wherein
the pillar further includes a gate insulation layer and a charge storage layer, and
the first conductive layer is electrically connected to the semiconductor layer in the pillar.
8. The semiconductor memory device according to claim 1 , wherein
the pillar further includes a gate insulation layer and a charge storage layer, and
adjacent portions of the plurality of second conductive layers, the gate insulation layer, the semiconductor layer, and the charge storage layer constitute memory cells.
9. The semiconductor memory device according to claim 1 , wherein
the slit isolates adjacent portions of the plurality of second conductive layers in the third direction.
10. The semiconductor device according to claim 1 , wherein the slit includes a conductive layer extending in the first direction and the second direction and a plurality of insulating layers on outer sides of the conductive layer in the third direction.
11. A method of manufacturing a semiconductor memory device, comprising:
forming a first conductive layer on a substrate;
forming a first sacrificial layer on the first conductive layer;
forming a second conductive layer on the first sacrificial layer;
removing a portion of the second conductive layer to form a first groove therethrough that reaches the first sacrificial layer;
forming a second sacrificial layer in the first groove;
alternately stacking a plurality of second insulating layers and a plurality of third insulating layers on the second conductive layer and the second sacrificial layer;
removing a portion of the second insulating layers and the third insulating layers to form a second groove that reaches the second sacrificial layer;
removing the second sacrificial layer and the first sacrificial layer via the second groove to form a cavity on the first conductive layer; and
forming a third conductive layer in the cavity.
12. The method according to claim 11 , further comprising forming a third insulating layer on the sidewalls of the first groove before forming the second sacrificial layer in the first groove.
13. The method according to claim 12 , further comprising forming a fourth insulating layer on the sidewalls of the second groove before removing the first and second sacrificial layers.
14. The method according to claim 13 , further comprising:
removing the third and fourth insulating layers; and
removing the third insulating layers with an etchant via the second groove to form gaps between adjacent second insulating layers.
15. The method according to claim 14 , further comprising forming a conductor in the gaps between adjacent second insulating layers.
16. The method according to claim 11 , wherein the first groove is wider in a first direction of the surface of the substrate than an adjoining part of the second groove in the first direction.
17. The method according to claim 11 , wherein a portion of the first groove extends along the substrate facing a side of the second insulating layer closest to the substrate.