IP Library Granted Patent US 10,319,070
Granted Patent B2
US 10,319,070 · App. 16/120,591 · Granted Jun 11, 2019

Dynamic page sizing of page table entries

Inventors: Abhishek R. Appu (El Dorado Hills, CA); Joydeep Ray (Folsom, CA); Altug Koker (El Dorado Hills, CA); Balaji Vembu (Folsom, CA); Prasoonkumar P. Surti (Folsom, CA); Kamal Sinha (Rancho Cordova, CA); Vasanth Ranganathan (El Dorado Hills, CA); Kiran C. Veernapu (Bangalore, IN); Bhushan M. Borole (Rancho Cordova, CA); Wenyin Fu (Folsom, CA)
Assignee: Intel Corporation
G06T1/60G06T1/20G06T15/005
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Quick Facts
Patent No.
US 10,319,070
App. No.
16/120,591
Granted
Jun 11, 2019
Kind
B2
Abstract

In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.

Claims (33)

1. An apparatus comprising:

a graphics processor;

a graphics driver to receive a memory block allocation and, in response to said allocation, to set a page table entry to indicate a variable page table block size to match a size of the allocation; and

a memory coupled to said processor.

2. The apparatus of claim 1 , said graphics driver to set the page table entry to indicate the block size.

3. The apparatus of claim 1 , said graphics driver to use a base memory unit size and to specify a multiple of said size as the variable page table block size in a page table entry.

4. The apparatus of claim 3 wherein said base memory unit size is 4 KB.

5. The apparatus of claim 1 wherein said graphics driver to dynamically indicate said page table block size in multiples of 4 KB.

6. The apparatus of claim 1 , said graphics driver to dynamically indicate one of at least four selectable variable page table block sizes.

7. The apparatus of claim 1 , said graphics driver to indicate the page table block size at a size other than 4 KB, 64 KB, or 2 MB.

8. The apparatus of claim 1 , said graphics driver to indicate the page table entry size to reduce the number of translation lookaside buffer entries.

9. A system comprising:

a graphics processor;

a graphics driver to receive a memory block allocation and, in response to said allocation, to set a page table entry to indicate a variable page table block size to match a size of the allocation;

a memory coupled to said graphics processor; and

a central processing unit to provide said memory block allocation to said graphics driver.

10. The system of claim 9 , said graphics driver to set the page table entry to indicate the block size.

11. The system of claim 9 , said graphics driver to use a base memory unit size and to specify a multiple of said size as the variable page table block size in a page table entry.

12. The system of claim 11 wherein said base memory unit size is 4 KB.

13. The system of claim 9 wherein said graphics driver to dynamically indicate said page table block size in multiples of 4 KB.

14. The system of claim 9 , said graphics driver to dynamically indicate one of at least four selectable variable page table block sizes.

15. The system of claim 9 , said graphics driver to indicate the page table block size at a size other than 4 KB, 64 KB, or 2 MB.

16. The system of claim 9 , said graphics driver to indicate the page table entry size to reduce the number of translation lookaside buffer entries.

17. One or more non-transitory computer readable media storing instructions to perform a sequence comprising:

receiving a request for a page table size based on a size of memory block allocation; and

in response to said allocation, setting a page table entry to indicate a variable page table block size to match the allocation size.

18. The media of claim 17 , said media storing instructions to perform a sequence including setting the page table entry to indicate that allocation size.

19. The media of claim 17 , said media storing instructions to perform a sequence including using a base memory unit size and to specify a multiple of said size as the variable page table block size in a page table entry.

20. The media of claim 19 , said media storing instructions to perform a sequence further storing instructions to perform a sequence wherein said base memory unit size is 4 KB.

21. The media of claim 17 , said media storing instructions to perform a sequence including dynamically setting said page table block size in multiples of 4 KB.

22. The media of claim 17 , said media storing instructions to perform a sequence including dynamically setting one of at least four selectable variable page table block sizes.

23. The media of claim 17 , said media storing instructions to perform a sequence including setting the page table block size at a size other than 4 KB, 64 KB, or 2 MB.

24. The media of claim 17 , said media storing instructions to perform a sequence including setting the page table entry size to reduce the number of translation lookaside buffer entries.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2022
From: INTEL CORPORATION
To: UNM RAINFOREST INNOVATIONS
Reel/Frame 060234/0794 →
Continuity (2)
Continuation 15483059 · Apr 10, 2017
Related Publication 20190026856A1 · Jan 24, 2019