IP Library Granted Patent US 10,585,837
Granted Patent B2
US 10,585,837 · App. 16/120,735 · Granted Mar 10, 2020

Data transmission method and data transmission system

Inventors: Alan Kobayashi (Los Altos, CA); Sujan Valiyaka Thomas (Pleasanton, CA); Ramakrishna Chilukuri (San Jose, CA); Rahul Kumar Agarwal (Saratoga, CA); Iyothsna Nagaraja (San Jose, CA)
Assignee: MegaChips Technology America Corporation
G06F13/42H03M13/1515
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,585,837
App. No.
16/120,735
Granted
Mar 10, 2020
Kind
B2
Abstract

A data transmission method and system for enhanced channel coding efficiency of a DisplayPort interface is disclosed. One method comprises transmitting a plurality of coding units for each micro-packet in each of one or more lanes of a DisplayPort Main Link from a DisplayPort transmitter, wherein each of the coding units comprises: a group of m symbol chunks, each symbol chunk including four 8-bit symbols, wherein in is 2 or 4; and an n-bit code data indicator that precedes the group of m-symbol chunks, wherein n is 2 or 4, and wherein the n-bit code data indicator indicates a content type of the m symbol chunks.

Claims (53)

1. A data transmission method for enhanced channel coding efficiency of a DisplayPort interface, the method comprising:

transmitting a plurality of coding units for each micro-packet in each of one or more lanes of a DisplayPort Main Link from a DisplayPort transmitter, wherein each of the coding units comprises

a group of m symbol chunks, each symbol chunk including four 8-bit symbols, wherein m is 2 or 4, each symbol chunk having each content type; and

an n-bit code data indicator that precedes the group of m-symbol chunks, wherein n is 2 or 4, and wherein the n-bit code data indicator indicates the content type of the m symbol chunks.

2. The method of claim 1 , wherein

the content type is a data link symbol, or one or more of a control link symbol, a Reed Solomon (RS) parity symbol and a PHY sync symbol.

3. The method of claim 1 , wherein

eight coding units per lane are transmitted for each micro-packet in each of four lanes of the DisplayPort Main Link.

4. The method of claim 1 , wherein

16 coding units per lane are transmitted for each micro-packet in each of two lanes of the DisplayPort Main Link.

5. The method of claim 1 , wherein

32 coding units per lane are transmitted for each micro-packet in a single lane of the DisplayPort Main Link.

6. A data reception method for enhanced channel coding efficiency of a DisplayPort interface, the method comprising:

receiving a plurality of coding units for each micro-packet in each of one or more lanes of a DisplayPort Main Link from a DisplayPort transmitter, wherein each of the coding units comprises

a group of m symbol chunks, each symbol chunk including four 8-bit symbols, wherein m is 2 or 4, each symbol chunk having each content type; and

an n-bit code data indicator that precedes the group of m-symbol chunks, wherein n is 2 or 4, and wherein the n-bit code data indicator indicates the content type of the m symbol chunks.

7. The method of claim 6 , wherein

the content type is a data link symbol, or one or more of a control link symbol, a Reed Solomon (RS) parity symbol and a PHY sync symbol.

8. The method of claim 6 , wherein

eight coding units per lane are received for each micro-packet in each of four lanes of the DisplayPort Main Link.

9. The method of claim 6 , wherein

16 coding units per lane are received for each micro-packet in each of two lanes of the DisplayPort Main Link.

10. The method according to claim 6 , wherein

32 coding units per lane are received for each micro-packet in a single lane of the DisplayPort Main Link.

11. A transmission device for a DisplayPort interface comprising:

one or more lane serializer-drivers; and

a PHY logical sub-layer configured to arrange and transmit stream data to the one or more lane serializer-drivers, wherein the stream data comprises a plurality of coding units for each micro-packet directed to each of the one or more lane serializer-drivers, and wherein each of the coding units comprises

a group of m symbol chunks, each symbol chunk including four 8-bit symbols, wherein m is 2 or 4, each symbol chunk having each content type; and

an n-bit code data indicator that precedes the group of m-symbol chunks, wherein n is 2 or 4, and wherein the n-bit code data indicator indicates the content type of the m symbol chunks.

12. The transmission device of claim 11 , wherein

the content type is a data link symbol, or one or more of a control link symbol, a Reed Solomon (RS) parity symbol and a PHY sync symbol.

13. The transmission device of claim 11 , wherein

eight coding units per lane are transmitted for each micro-packet in each of four lanes of the DisplayPort Main Link.

14. The transmission device of claim 11 , wherein

16 coding units per lane are transmitted for each micro-packet in each of two lanes of the DisplayPort Main Link.

15. The transmission device of claim 11 , wherein

32 coding units per lane are transmitted for each micro-packet in a single lane of the DisplayPort Main Link.

16. The transmission device of claim 11 , further comprising:

one or more High-bandwidth Digital Content Protection (HDCP) encryption circuits communicatively coupled to the PHY logical sub-layer element for encrypting stream data.

17. The transmission device of claim 11 , wherein

the PHY logical sub-layer is further configured to perform Reed Solomon Forward Error Correction on the stream data.

18. A reception device for a DisplayPort interface comprising:

a receiver configured to receive a plurality of coding units for each micro-packet in each of one or more lanes of a DisplayPort Main Link from a DisplayPort transmitter, wherein each of the coding units comprises

a group of m symbol chunks, each symbol chunk including four 8-bit symbols, wherein m is 2 or 4, each symbol chunk having each content type; and

an n-bit code data indicator that precedes the group of m-symbol chunks, wherein n is 2 or 4, and wherein the n-bit code data indicator indicates the content type of the m symbol chunks.

19. The reception device of claim 18 , wherein

the content type is a data link symbol, or one or more of a control link symbol, a Reed Solomon (RS) parity symbol and a PHY sync symbol.

20. The reception device of claim 18 , wherein

eight coding units per lane are received for each micro-packet in each of four lanes of the DisplayPort Main Link.

21. The reception device of claim 18 , wherein

16 coding units per lane are received for each micro-packet in each of two lanes of the DisplayPort Main Link.

22. The reception device of claim 18 , wherein

32 coding units per lane are received for each micro-packet in a single lane of the DisplayPort Main Link.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2024
From: KINETIC TECHNOLOGIES INTERNATIONAL HOLDINGS LP
To: AY DEE KAY LLC DBA INDIE SEMICONDUCTOR
Reel/Frame 068037/0425 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2023
From: NAGARAJA, JYOTHSNA
To: KINETIC TECHNOLOGIES INTERNATIONAL HOLDINGS LP
Reel/Frame 065514/0801 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2023
From: AGARWAL, RAHUL KUMAR
To: KINETIC TECHNOLOGIES INTERNATIONAL HOLDINGS LP
Reel/Frame 065515/0088 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 30, 2022
From: KINETIC TECHNOLOGIES
To: KINETIC TECHNOLOGIES INTERNATIONAL HOLDINGS LP
Reel/Frame 059852/0228 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2020
From: KOBAYASHI, ALAN; THOMAS, SUJAN VALIYAKA; CHILUKURI, RAMAKRISHNA
To: MEGACHIPS TECHNOLOGY AMERICA CORPORATION
Reel/Frame 054686/0997 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2020
From: KOBAYASHI, ALAN; THOMAS, SUJAN VALIYAKA; CHILUKURI, RAMAKRISHNA
To: MEGACHIPS TECHNOLOGY AMERICA CORPORATION
Reel/Frame 054687/0051 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2020
From: KOBAYASHI, ALAN; THOMAS, SUJAN VALIYAKA; CHILUKURI, RAMAKRISHNA
To: MEGACHIPS TECHNOLOGY AMERICA CORPORATION
Reel/Frame 054687/0092 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2020
From: MEGACHIPS TECHNOLOGY AMERICA CORPORATION
To: KINETIC TECHNOLOGIES
Reel/Frame 051756/0475 →