IP Library Granted Patent US 11,476,240
Granted Patent B2
US 11,476,240 · App. 16/120,738 · Granted Oct 18, 2022

Semiconductor device

Inventor: Mariko Oishi (Yokohama, JP)
Assignee: Kioxia Corporation
H01L25/18H01L23/3121H01L24/32H01L24/33H01L24/48H01L24/73H01L25/0657H01L2224/2919H01L2224/32145H01L2224/32225H01L2224/33181H01L2224/48091H01L2224/48106H01L2224/48145H01L2224/48227H01L2224/73215H01L2224/73265H01L2225/0651H01L2225/06506H01L2225/06562H01L2225/06575H01L2225/06582H01L2924/0635H01L2924/0665H01L2924/07025H01L2924/10253H01L2924/1438H01L2924/14511
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Quick Facts
Patent No.
US 11,476,240
App. No.
16/120,738
Granted
Oct 18, 2022
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes a board, a first member, a first adhesive layer, a first electronic component, a second electronic component, and a resin. The board includes a first surface. The first member includes a second surface, and a third surface made of a material including a first organic material. The first adhesive layer adheres to the first surface and the second surface. The first electronic component is attached to the first surface, and embedded in the first adhesive layer. The resin in which the first member, the first adhesive layer, and the second electronic component embedded adheres to the first surface and the third surface.

Claims (41)

1. A semiconductor device comprising:

a board including a first surface;

a first member that is a laminate including a silicon substrate and a resin layer including polyimide, the first member having a second surface facing the first surface, and the resin layer having a third surface;

a first adhesive layer positioned between the first surface and the second surface and adhering directly to the first surface and the entire second surface;

a first semiconductor chip positioned between the first surface and the second surface, attached to the first surface, and embedded in the first adhesive layer;

a second semiconductor chip including an eighth surface that is a lower surface of the second semiconductor chip, the eighth surface facing the third surface;

a second adhesive layer positioned between the third surface and the eighth surface and adhering to the third surface and the entire eighth surface;

a resin in which the first member, the first adhesive layer, and the second semiconductor chip embedded, the resin adhering to the first surface and the third surface; and

a first bonding wire electrically and physically connecting the second semiconductor chip to the board and embedded in the resin, wherein

in plane view looking toward a direction in which the second surface is oriented, the first semiconductor chip is smaller than the first member and is positioned inside an edge of the first member,

in plane view looking toward a direction in which the second surface is oriented, the second semiconductor chip is smaller than the first member and is positioned inside an edge of the first member,

in plane view looking toward a direction in which the second surface is oriented, the second semiconductor chip is larger than the first semiconductor chip,

the first member is not provided with any conductive pattern therein and not connected to any bonding wire, and

in a plane view toward a direction in which the second surface is oriented, the second adhesive layer is smaller than the resin layer of the first member.

2. The semiconductor device according to claim 1 , wherein

the first member includes a fourth surface positioned between the second surface and the third surface,

the resin adheres further to the fourth surface, and

an area of a portion of the third surface to which the resin adheres is larger than an area of a portion of the fourth surface to which the resin adheres.

3. The semiconductor device according to claim 1 , wherein

the first member includes an intermediate layer positioned between the silicon substrate and the resin layer and positioned between the second semiconductor chip and the silicon substrate,

the resin layer adheres to the intermediate layer, and

a tensile strength of a connecting portion between the resin layer and the intermediate layer is larger than a tensile strength of a connecting portion between the resin layer and the silicon substrate, which is obtained in a case where the resin layer adheres to the silicon substrate.

4. The semiconductor device according to claim 1 , wherein

the first member includes an intermediate layer positioned between the silicon substrate and the resin layer and made of a material including oxide or nitride of the silicon substrate.

5. The semiconductor device according to claim 1 , wherein the second semiconductor chip includes a layer made of a silicon substrate.

6. The semiconductor device according to claim 1 , wherein the second semiconductor chip includes a surface made of a material including the polyimide.

7. The semiconductor device according to claim 1 , wherein the resin is made of a material including the polyimide.

8. The semiconductor device according to claim 1 , wherein

the second semiconductor chip includes a flash memory, and

the first semiconductor chip includes a controller that controls the flash memory.

9. The semiconductor device according to claim 1 , wherein the first adhesive layer includes a Die Attach Film.

10. The semiconductor device according to claim 1 , further comprising a second bonding wire electrically connecting the first semiconductor chip to the board and embedded in the first adhesive layer.

11. The semiconductor device according to claim 1 , wherein a material of the second adhesive layer is different from a material of the resin layer.

12. The semiconductor device according to claim 1 , further comprising a second member embedded in the resin,

wherein

the second semiconductor chip includes a plurality of third semiconductor chips mutually stacked,

the second member is positioned between two of the plurality of third semiconductor chips adjacent to each other, and includes a fifth surface to which one of the plurality of third semiconductor chips is attached, a sixth surface to which another one of the plurality of third semiconductor chips is attached, and a seventh surface positioned between the fifth surface and the sixth surface and made of a material including an organic material, and

the resin adheres further to the seventh surface.

13. The semiconductor device according to claim 12 , further comprising a plurality of second adhesive layers including the second adhesive layer positioned between the third surface and the eighth surface,

wherein each of the plurality of second adhesive layers attaches one of the plurality of third semiconductor chips to another one of the plurality of third semiconductor chips, the third surface, or the second member.

14. The semiconductor device according to claim 13 , wherein the plurality of second adhesive layers include Die Attach Films.

Assignments (2)
CHANGE OF NAME Recorded Jan 21, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058805/0801 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2018
From: OISHI, MARIKO
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 046777/0833 →
Priority Claims (1)
JP JP2018-035714 · Feb 28, 2018 · national
Continuity (1)
Related Publication 20190267364A1 · Aug 29, 2019