IP Library Patent Application 16120991
Patent Application
App. No. 16/120,991

INTERCONNECTS FOR A MULTI-DIE PACKAGE

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Quick Facts
Patent No.
US None
App. No.
16/120,991
Abstract

Systems, devices, and methods for interconnects for a multi-die package are described. A multi-die package may include a set of conductive pillars and two or more semiconductor dice that each include a bond pad. In some cases, the multi-die package may include a plurality of pillar-wire combinations, and a bond wire may couple a corresponding conductive pillar with a corresponding bond pad. Pillar-wire combinations may each collectively have a matched impedance, or pillar-wire combinations in different groups may have different collective impedances. In other cases, a conductive pillar may be directly coupled with a corresponding bond pad without a bond wire. Different pillar-wire combinations or directly-coupled pillars may carry different signals. In some cases, pillars may be individually impedance-matched to a desired impedance.

Claims (65)

1 . An apparatus, comprising:

a plurality of semiconductor dice disposed above a substrate, each semiconductor die of the plurality comprising an upper surface in contact with a bond pad;

a plurality of conductive pillars above the substrate; and

a plurality of bond wires each coupled with a corresponding conductive pillar of the plurality and a corresponding bond pad.

2 . The apparatus of claim 1 , wherein:

the plurality of bond wires and the plurality of conductive pillars comprise a plurality of pillar-wire combinations that each comprise a bond wire of the plurality and the corresponding conductive pillar, and

the pillar-wire combinations of the plurality each have a matched impedance.

3 . The apparatus of claim 2 , wherein the plurality of conductive pillars comprises:

conductive pillars that each have a matched impedance.

4 . The apparatus of claim 2 , wherein the plurality of conductive pillars comprises:

a first conductive pillar of the plurality that has a different impedance than a second conductive pillar of the plurality.

5 . The apparatus of claim 1 , wherein:

a conductive pillar of the plurality has a height that is greater than or equal to a thickness of a semiconductor die of the plurality.

6 . The apparatus of claim 1 , wherein the plurality of conductive pillars comprises:

a first group of conductive pillars having a first height and a second group of conductive pillars having a second height different from the first height.

7 . The apparatus of claim 1 , wherein the plurality of conductive pillars comprises:

a first group of conductive pillars having a first cross-sectional area and a second group of conductive pillars having a second cross-sectional area different from the first cross-sectional area.

8 . The apparatus of claim 1 , wherein the plurality of conductive pillars comprises:

groups of conductive pillars, each group of conductive pillars corresponding to a respective semiconductor die of the plurality.

9 . The apparatus of claim 1 , wherein:

the plurality of bond wires and the plurality of conductive pillars comprise a plurality of pillar-wire combinations that each comprise a bond wire of the plurality and the corresponding conductive pillar; and

the plurality of pillar-wire combinations comprises groups of pillar-wire combinations, pillar-wire combinations in different groups of pillar-wire combinations having different impedances.

10 . The apparatus of claim 9 , wherein:

a first group of pillar-wire combinations is configured to communicate a first category of signals and a second group of pillar-wire combinations is configured to communicate a second category of signals.

11 . The apparatus of claim 10 , wherein:

the first category of signals comprises a power signal and the second category of signals comprises a clock signal or a data signal.

12 . The apparatus of claim 1 , wherein:

the plurality of semiconductor dice comprises a stack of semiconductor dice; and

a subset of the semiconductor dice of the stack are offset in a first direction.

13 . The apparatus of claim 12 , wherein:

a first semiconductor die of the plurality is offset relative to a second semiconductor die of the plurality in the first direction; and

a third semiconductor die of the plurality is offset relative to the second semiconductor die of the plurality in a second direction that is opposite to the first direction.

14 . The apparatus of claim 12 , wherein:

the subset of the semiconductor dice of the stack are offset in a second direction that is orthogonal to the first direction.

15 . The apparatus of claim 12 , wherein:

the plurality of conductive pillars is disposed above a first region of the substrate;

the stack of semiconductor dice is disposed above a second region of the substrate; and

each semiconductor die of the stack is disposed farther from the first region than any lower semiconductor die of the stack.

16 . An apparatus, comprising:

a plurality of semiconductor dice disposed above a first region of a substrate, each semiconductor die of the plurality comprising a lower surface in contact with a bond pad; and

a plurality of conductive pillars above a second region of the substrate, the second region being subset of the first region, each conductive pillar of the plurality directly coupled with a corresponding bond pad.

17 . The apparatus of claim 16 , wherein conductive pillars of the plurality are impedance-matched to one another.

18 . The apparatus of claim 17 , wherein:

a first conductive pillar of the plurality has a different height than a second conductive pillar of the plurality.

19 . The apparatus of claim 17 , wherein:

a first conductive pillar of the plurality has a different cross-sectional area than a second conductive pillar of the plurality.

20 . The apparatus of claim 16 , wherein:

the plurality of conductive pillars further comprises groups of conductive pillars; and

a height of conductive pillars in a same group of conductive pillars corresponds to a distance between the substrate and the lower surface of a corresponding semiconductor die of the plurality.

21 . The apparatus of claim 16 , wherein:

each conductive pillar of the plurality is electrically coupled with the corresponding bond pad via a solder.

22 . An apparatus, comprising:

a plurality of semiconductor dice disposed above a substrate, each semiconductor die of the plurality comprising a bond pad of a plurality of bond pads;

a plurality of conductive pillars disposed above the substrate, wherein a first group of conductive pillars of the plurality has a first height that is less than a thickness of a semiconductor die of the plurality and a second group of conductive pillars of the plurality has a second height that is greater than the thickness of the semiconductor die; and

a plurality of bond wires each electrically coupling a corresponding conductive pillar of the plurality with a corresponding bond pad of the plurality.

23 . The apparatus of claim 16 , wherein:

conductive pillars of the plurality are impedance-matched to a common impedance.

24 . An apparatus, comprising:

a plurality of semiconductor dice disposed above a first region of a substrate, each semiconductor die of the plurality comprising a bond pad; and

a plurality of conductive pillars disposed above a second region of the substrate, the first region at least partially including the second region, wherein:

each conductive pillar of a first group of conductive pillars of the plurality has a first height corresponding to a first distance between a first semiconductor die of the plurality and the substrate; and

each conductive pillar of a second group of conductive pillars of the plurality has a second height corresponding to a second distance between a second semiconductor die of the plurality and the substrate.

25 . The apparatus of claim 16 , wherein:

each conductive pillar of the first group is in contact with the first semiconductor die; and

each conductive pillar of the second group is in contact with the second semiconductor die.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051028/0835 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050719/0550 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2019
From: KIM, KANG-YONG; YOO, CHAN; LIM, DONG SOON; SONG, JAEKYU
To: MICRON TECHNOLOGY, INC.
Reel/Frame 049340/0470 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.., AS COLLATERAL AGENT
Reel/Frame 047630/0756 →
SUPPLEMENT NO. 10 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048102/0420 →