SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
1 . A semiconductor memory device comprising:
an array chip including a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells and not including a substrate;
a circuit chip including a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit, the circuit chip being stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer;
a bonding metal provided between the memory-side interconnection layer and the circuit-side interconnection layer, and bonded to the memory-side interconnection layer and the circuit-side interconnection layer;
a pad provided in the array chip; and
an external connection electrode reaching the pad from a surface side of the array chip.
2 . The device according to claim 1 , wherein
the array chip includes:
a stacked body including a plurality of electrode layers stacked via an insulating layer;
a semiconductor body extending in a stacking direction of the stacked body in the stacked body;
a charge storage film provided between the semiconductor body and the electrode layers;
a plurality of bit lines connected to an end portion of the semiconductor body; and
a source line connected to another end portion of the semiconductor body.
3 . The device according to claim 2 , wherein
the electrode layers are formed in a step shape at an end of a memory cell array region where the memory cells are disposed, and
the memory-side interconnection layer includes word interconnection layers connected to the electrode layers formed in the step shape.
4 . The device according to claim 3 , wherein
the bonding metal includes a plurality of bit-line lead-out sections electrically connected to the bit lines, and
the bit-line lead-out sections are disposed in a region overlapping the memory cell array region in the stacking direction.
5 . The device according to claim 3 , wherein
the bonding metal includes a plurality of word-line lead-out sections electrically connected to the word interconnection layers, and
the pad is provided in a region overlapping the word-line lead-out sections in the stacking direction.
6 . The device according to claim 2 , wherein the pad is provided in a same layer as the source line and formed of a same material as the source line.
7 . The device according to claim 3 , wherein the pad is provided in a same layer as the word interconnection layers and formed of a same material as the word interconnection layers.
8 . The device according to claim 2 , wherein
a gate layer is provided in a layer on an opposite side of the memory-side interconnection layer in the stacked body, and
the pad is formed in a same layer as the gate layer and formed of a same material as the gate layer.
9 . The device according to claim 1 , further comprising an insulating film provided around the bonding metal.
10 . A semiconductor memory device comprising:
an array chip including a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells and not including a substrate;
a circuit chip including a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit, the circuit chip being stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer;
a bonding metal provided between the memory-side interconnection layer and the circuit-side interconnection layer, and bonded to the memory-side interconnection layer and the circuit-side interconnection layer;
a pad provided in the circuit chip; and
an external connection electrode reaching the pad from a surface side of the array chip.
11 . The device according to claim 10 , wherein
the array chip includes:
a stacked body including a plurality of electrode layers stacked via an insulating layer;
a semiconductor body extending in a stacking direction of the stacked body in the stacked body;
a charge storage film provided between the semiconductor body and the electrode layers;
a plurality of bit lines connected to an end portion of the semiconductor body; and
a source line connected to another end portion of the semiconductor body.
12 . The device according to claim 11 , wherein
the electrode layers are formed in a step shape at an end of a memory cell array region where the memory cells are disposed, and
the memory-side interconnection layer includes word interconnection layers connected to the electrode layers formed in the step shape.
13 . The device according to claim 12 , wherein
the bonding metal includes a plurality of bit-line lead-out sections electrically connected to the bit lines, and
the bit-line lead-out sections are disposed in a region overlapping the memory cell array region in the stacking direction.
14 . The device according to claim 10 , wherein the pad is provided in a same layer as the circuit-side interconnection layer and formed of a same material as the circuit-side interconnection layer.
15 . The device according to claim 10 , further comprising an insulating film provided around the bonding metal.
16 . A semiconductor memory device comprising:
an array chip including a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells and not including a substrate;
a circuit chip including a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit, the circuit chip being stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer; and
a bonding metal provided between the memory-side interconnection layer and the circuit-side interconnection layer, and bonded to the memory-side interconnection layer and the circuit-side interconnection layer;
the circuit chip including a pad, and
the array chip including a via hole penetrating through the array chip and reaching the pad.
17 . The device according to claim 16 , wherein
a plurality of semiconductor memory chips each including the array chip, the circuit chip, and bonding metal is stacked,
each of the semiconductor memory chips includes an end portion along one side of the semiconductor memory chip, and
a plurality of the pad and a plurality of the via holes are arrayed in the end portion along the one side.
18 . The device according to claim 16 , wherein the circuit chip is
a combined control circuit chip including a control circuit and a solid state drive controller.