Source follower-based sensing scheme
Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.
1. An apparatus, comprising:
a first source follower coupled with a digit line of a memory cell and configured to output a first signal that is representative of a logic state stored by the memory cell;
a first switching component coupled with a sense component and an output of the first source follower, the first switching component configured to establish a conductive path between the first source follower and the sense component;
a second source follower coupled with a reference voltage supply and configured to output a second signal that is representative of a reference voltage provided by the reference voltage supply, the second source follower sharing a node with the first source follower;
a second switching component coupled with the sense component and an output of the second source follower, the second switching component configured to establish a second conductive path between the second source follower and the sense component; and
the sense component coupled with the first source follower and the second source follower and configured to sense a voltage difference between the first signal and the second signal.
2. The apparatus of claim 1 , further comprising:
a third switching component coupled with the first switching component, the first and third switching components sharing a first set of common nodes; and
a fourth switching component coupled with the second switching component, the second and fourth switching components sharing a second set of common nodes.
3. The apparatus of claim 1 , further comprising:
a third switching component coupled with the first source follower, wherein the third switching component is between the first source follower and the digit line.
4. The apparatus of claim 1 , further comprising:
a third switching component coupled with the first and second source followers and configured to isolate an output of the first source follower from an output of the second source follower.
5. An apparatus, comprising:
a first source follower coupled with a digit line of a memory cell and configured to output a first signal that is representative of a logic state stored by the memory cell, wherein an input of the first source follower is coupled with the digit line;
a second source follower coupled with a reference voltage supply and configured to output a second signal that is representative of a reference voltage provided by the reference voltage supply, wherein the second source follower shares a node with the first source follower and wherein an input of the second source follower is coupled with the reference voltage supply; and
a sense component coupled with the first source follower and the second source follower and configured to sense a voltage difference between the first signal and the second signal.
6. The apparatus of claim 1 , further comprising:
a voltage source coupled with the node shared by the first source follower and the second source follower, the voltage source configured to maintain a voltage of the node at a level.
7. A method, comprising:
generating a first signal at an output of a first source follower, the first signal representing a logic state stored by a memory cell;
generating a second signal at an output of a second source follower coupled with the first source follower, the second signal representing a reference voltage;
activating a first switching component coupled with the first source follower and a sense component;
activating a second switching component coupled with the second source follower and the sense component;
transferring the first signal to a sense component concurrent with transferring the second signal to the sense component, wherein transferring the first signal is based on activating the first switching component and transferring the second signal is based on activating the second switching component; and
determining the logic state stored by the memory cell based at least in part on sensing a voltage difference between the first signal and the second signal using the sense component.
8. The method of claim 7 , wherein generating the first signal comprises: generating the first signal concurrent with generating the second signal.
9. The method of claim 7 , further comprising:
establishing a first conductive path between the first source follower and the sense component; and
establishing a second conductive path between the second source follower and the sense component.
10. The method of claim 7 , further comprising:
deactivating a third switching component coupled with a digit line of the memory cell and the first source follower before transferring the first signal and the second signal.
11. A method, comprising:
supplying a first source follower with a first voltage that is based at least in part on a voltage of a digit line of a memory cell;
generating a first signal at an output of the first source follower, wherein the first signal represents a logic state stored by the memory cell and wherein an amplitude of the first signal is based at least in part on the first voltage;
supplying a second source follower with a second voltage that is based at least in part on a reference voltage;
generating a second signal at an output of the second source follower, wherein the second source follower is coupled with the first source follower, the second signal represents the reference voltage, and an amplitude of the second signal is based at least in part on the second voltage;
transferring the first signal to a sense component concurrent with transferring the second signal to the sense component; and
determining the logic state stored by the memory cell based at least in part on sensing a voltage difference between the first signal and the second signal using the sense component.
12. The method of claim 7 , further comprising:
modifying a voltage applied to a third switching component coupled with the first source follower, wherein the first signal is developed based at least in part on modifying the voltage.
13. The method of claim 7 , wherein the first source follower and the second source follower share a common node.
14. The method of claim 7 , wherein transferring the second signal overlaps at least partially in time with transferring the first signal.
15. A method, comprising:
modifying a first voltage applied to a first switching component that is coupled with a first source follower and a sense component, wherein modifying the first voltage activates the first switching component and establishes a first conductive path between the first source follower and the sense component;
modifying a second voltage applied to a second switching component that is coupled with a second source follower and the sense component, wherein modifying the second voltage activates the second switching component concurrent with activating the first switching component and establishes a second conductive path between the second source follower and the sense component; and
sensing, by the sense component, a voltage difference between a first signal received from the first source follower after activating the first switching component and a second signal received from the second source follower after activating the second switching component.
16. The method of claim 15 , further comprising:
reducing, before activating the first and second switching components, a voltage applied to a third switching component that is coupled with the first switching component and a digit line of a memory cell.
17. The method of claim 15 , wherein the first signal is received via a third switching component that couples the first switching component to the sense component and the second signal is received via a fourth switching component that couples the second switching component to the sense component.
18. The method of claim 17 , wherein an output of the first source follower and an output of the second source follower are separated from each other by the third switching component.
19. The method of claim 15 , wherein receiving the first signal comprises receiving the first signal via the first conductive path and wherein receiving the second signal comprising is received via the second conductive path.