Apparatuses and method for trimming input buffers based on identified mismatches

1. An apparatus comprising:

an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal, wherein the first input stage circuit comprises a plurality of serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage, wherein each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal; and

a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components; wherein the trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.

2. The apparatus of claim 1 , wherein a first transistor of a first pair of the plurality of serially-coupled transistor pairs is configured to receive the input signal and a second transistor of the first pair of the plurality of serially-coupled transistor pairs is configured to receive a first enable signal, wherein a first programmable component of the plurality of programmable components of the trim circuit is configured to provide the first enable signal.

3. The apparatus of claim 2 , wherein the first programmable component is configured to provide a control voltage on to the first enable signal when programmed, wherein the second transistor is enabled via the first enable signal having the control voltage.

4. The apparatus of claim 3 , wherein the first programmable component is a fuse and the second transistor is an n-type transistor or wherein the first programmable component is an anti-fuse and the second transistor is a p-type transistor.

5. The apparatus of claim 3 , wherein the trim circuit is further configured to be coupled to other enable signals during a mismatch detection operation.

6. The apparatus of claim 5 , wherein the other enable signals are selectively controlled via a testmode from a tester.

7. The apparatus of claim 1 , wherein the first input stage circuit comprises an additional transistor coupled between the output stage and the bias voltage and is configured to receive the input signal.

8. The apparatus of claim 1 , wherein the second input stage circuit comprises a second plurality of serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage, wherein each of the second plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal, the apparatus further comprising:

a second trim circuit coupled to the second input stage circuit and comprising a second plurality of programmable components; wherein the second trim circuit is configured to be programmed to provide the respective enable signals to the second input stage circuit based on a detected transition voltage offset relative to a target transition voltage.

9. The apparatus of claim 1 , wherein the first input stage circuit, the second input stage circuit, and the output stage form a differential amplifier.

10. The apparatus of claim 1 , wherein the output stage includes load circuitry.

11. The apparatus of claim 9 , wherein the load circuitry includes at least one of a current mirror or resistors or diodes.

12. An apparatus including:

a plurality of input buffers coupled to respective data pads to receive input signals and are each configured to receive a reference voltage and to provide an output voltage based on the reference voltage and the respective input signal; wherein each of the plurality of input buffers comprise a respective input stage that is configured to be adjusted to align respective transition voltages to a target transition voltage in response to respective enable signals; and

a plurality of trim circuits each coupled to a respective one of the plurality of input buffers, wherein each of the plurality of trim circuits comprises a respective plurality of programmable components that are configured to be programmed to provide the respective enable signals based on a respective detected transition voltage offset of the coupled input buffer relative to the target transition voltage.

13. The apparatus of claim 12 , wherein the respective input stage of each of the plurality of input buffers comprises a first input stage circuit and a second input stage circuit, wherein the first input stage circuit is configured to be adjusted to align the respective transition voltages to the target transition voltage in response to the respective enable signals, wherein each of the plurality of trim circuits further comprises a respective second plurality of programmable components that are configured to be programmed to provide the respective second enable signals based on the respective detected transition voltage offset of the coupled input buffer relative to the target transition voltage.

14. The apparatus of claim 13 , wherein the second input stage circuit is configured to be adjusted to align the respective transition voltages to the target transition voltage in response to respective second enable signals, wherein each of the plurality of trim circuits further comprises a respective second plurality of programmable components that are configured to be programmed to provide the respective second enable signals based on the respective detected transition voltage offset of the coupled input buffer relative to the target transition voltage.

15. The apparatus of claim 13 , wherein the first input stage circuit comprises a plurality of serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage and are enabled via the respective enable signals.

16. The apparatus of claim 13 , wherein the plurality of serially-coupled transistor pairs comprise n-type or p-type transistors.

17. A method comprising:

coupling a first input of an input buffer of a semiconductor device to a reference voltage and a second input of the input buffer to the reference voltage;

performing a series of write operations to store a respective state of an output signal of the input buffer based on a drive strength of the input buffer in a respective memory cell of a target row of memory cells;

adjusting the drive strength of the input buffer between each of the series of write operations;

incrementing the target row of memory cells between each of the series of write operations;

determining a transition voltage of the input buffer based on the stored state of the output signal in the memory cells corresponding to the series of write operations; and

programming a trim circuit coupled to an input stage of the input buffer to adjust the transition voltage to a target transition voltage.

18. The method of claim 17 , further comprising:

reading the stored state of the output signal from the memory cells corresponding to the series of write operations; and

determining a first memory cell of the memory cells having a different stored state than a previous memory cell; wherein the transition voltage is determined based on the test signal voltage for the write operation of the series of write operations associated with the first memory cell.

19. The method of claim 17 , wherein programming the trim circuit coupled to an input stage of the input buffer comprises selectively programming one or more programmable components of the trim circuit to adjust the transition voltage to the target transition voltage.

20. The method of claim 17 , wherein adjusting the drive strength of the input buffer includes adjusting the drive strength of only one side of the input buffer between each of the series of write operations.