First-pass dynamic program targeting (DPT)

1. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to:

determine that a first programming pass of a programming operation has been performed on a memory cell of the memory component; and

perform a dynamic program targeting (DPT) operation on the memory cell to calibrate a first program-verify (PV) target value that results in an adjustment to a placement of a first first-pass programming distribution and a second PV target value that results in an adjustment to a placement of a second first-pass programming distribution before a second programming pass of the programming operation is performed on the memory cell.

2. The system of claim 1 , wherein the processing device is further to:

perform a second DPT operation on the memory cell to calibrate a third PV target value that results in an adjustment to a placement of a third first-pass programming distribution before the second programming pass of the programming operation is performed on the memory cell.

3. The system of claim 1 , wherein the processing device is further to:

perform one or more DPT additional operations on the memory cell to calibrate a remaining PV target values that result in adjustments to placements of each of the remaining first-pass programming distributions before the second programming pass of the programming operation is performed on the memory cell.

4. The system of claim 1 , wherein the processing device is further to:

perform a second DPT operation on the memory cell to calibrate a third PV target value that results in an adjustment to a placement of a third first-pass programming distribution after the second programming pass of the programming operation is performed on the memory cell.

5. The system of claim 1 , wherein the processing device is further to:

measure a valley width between each pair of a plurality of first first-pass programming distributions;

determine a net-zero adjustment to at least two PV target values corresponding to the plurality of first-pass programming distributions; and

adjust the at least two PV target values according to the net-zero adjustment, wherein the at least two PV target values comprises the first PV target value and the second PV target value.

6. The system of claim 1 , wherein the processing device is further to:

calculate a difference error count between each pair of a plurality of first-pass programming distributions;

determine a first adjustment amount to the first PV target value and a second adjustment amount to the second PV target value based on the difference error counts;

adjust the first PV target value by the first adjustment amount; and

adjust the second PV target value by the second adjustment amount.

7. The system of claim 1 , wherein the memory component comprises a block comprising a plurality of memory cells organized in a plurality of wordline groups, wherein the memory cell is a sample cell of a first wordline group of the plurality of wordlines groups.

8. The system of claim 7 , wherein the block further comprises a second sample memory cell of a second wordline group of the plurality of wordlines groups, wherein the processing device is further to:

determine that the first programming pass has been performed on the second sample memory cell; and

perform a second DPT operation on the second sample memory cell to calibrate a third PV target value that results in an adjustment to a placement of a third first-pass programming distribution and a fourth PV target value that results in an adjustment to a placement of a fourth first-pass programming distribution before the second programming pass is performed on the second sample memory cell.

9. The system of claim 1 , wherein the memory component comprises a first block comprising the memory cell and a second block comprising a second memory cell, and wherein the processing device is further to:

determine that the first programming pass has been performed on the second memory cell; and

perform a second DPT operation on the second memory cell to calibrate a third PV target value that results in an adjustment to a placement of a third first-pass programming distribution and a fourth PV target value that results in an adjustment to a placement of a fourth first-pass programming distribution before the second programming pass is performed on the second memory cell.

10. The system of claim 1 , wherein the memory cell, after the first programming pass, comprises the first first-pass programming distribution, the second first-pass programming distribution, a third first-pass programming distribution, and a fourth first-pass programming distribution, wherein a third PV target value that results in an adjustment to a placement of the third first-pass programming distribution and a fourth PV target value that results in an adjustment to a placement of the fourth first-pass programming distribution are fixed while the first PV target value and the second PV target value are calibrated.

11. The system of claim 10 , wherein the memory cell, after the second programming pass, comprises eight second-pass programming distributions and eight PV target values.

12. The system of claim 1 , wherein:

the memory cell, after the first programming pass, comprises:

eight first-pass programming distributions including the first first-pass programming distribution and the second first-pass programming distribution; and

eight PV target values including the first PV target value and the second PV target value; and

the memory cell, after the second programming pass, comprises:

sixteen second-pass programming distributions; and

sixteen PV target values.

13. A method comprising:

initiating a block programming sequence on a block of a memory component, the block programming sequence comprising at least a first programming pass and a second programming pass;

during block programming of a first sample page stack in the block, interrupting the block programming sequence before the second programming pass is performed;

while the block programming sequence is interrupted, performing a dynamic program targeting (DPT) operation on the first sample page stack until at least two programming distributions of the first sample page stack are balanced; and

resuming the block programming sequence.

14. The method of claim 13 , further comprising sampling the first sample page stack to obtain a number of programming distributions comprising a first programming distribution, a last programming distribution, and a plurality of intervening programming distributions, wherein performing the DPT operation on the first sample page stack comprises performing the DPT operation on the first sample page stack until the plurality of intervening programming distributions are balanced between the first programming distribution and a second programming distribution.

15. The method of claim 13 , wherein the first sample page stack is in a first wordline group, and wherein the method further comprises:

during block programming of a second sample page stack in a second wordline group, interrupting the block programming sequence before the second programming pass of the second sample page stack is performed;

while the block programming sequence of the second sample page stack is interrupted, performing a second DPT operation on the second sample page stack until at least two programming distributions of the second sample page stack are balanced; and

resuming the block programming sequence.

16. The method of claim 13 , wherein the first sample page stack is in a first wordline group, and wherein the method further comprises:

initiating a second block programming sequence on a second block of the memory component, the second block programming sequence comprising at least a first programming pass and a second programming pass;

during block programming of a second sample page stack in a second wordline group in the second block, interrupting the second block programming sequence before the second programming pass of the second block programming sequence is performed;

while the second block programming sequence is interrupted, performing a second DPT operation on the second sample page stack until at least two programming distributions of the first sample page stack are balanced; and

resuming the second block programming sequence.

17. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

initiate a block programming sequence on a block of a memory component, the block programming sequence comprising at least a first programming pass and a second programming pass;

during block programming of a first sample page stack in the block, interrupt the block programming sequence before the second programming pass is performed;

while the block programming sequence is interrupted, perform a dynamic program targeting (DPT) operation on the first sample page stack until at least two programming distributions of the first sample page stack are balanced; and

resume the block programming sequence.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the processing device is further to:

sample the first sample page stack to obtain a number of programming distributions comprising a first programming distribution, a last programming distribution, and a plurality of intervening programming distributions; and

perform the DPT operation on the first sample page stack until the plurality of intervening programming distributions are balanced between the first programming distribution and a second programming distribution.

19. The non-transitory computer-readable storage medium of claim 17 , wherein the first sample page stack is in a first wordline group, and wherein the processing device is further to:

during block programming of a second sample page stack in a second wordline group, interrupt the block programming sequence before the second programming pass of the second sample page stack is performed;

while the block programming sequence of the second sample page stack is interrupted, perform a second DPT operation on the second sample page stack until at least two programming distributions of the second sample page stack are balanced; and

resume the block programming sequence.

20. The non-transitory computer-readable storage medium of claim 17 , wherein the first sample page stack is in a first wordline group, and wherein the processing device is further to:

initiate a second block programming sequence on a second block of the memory component, the second block programming sequence comprising at least a first programming pass and a second programming pass;

during block programming of a second sample page stack in a second wordline group in the second block, interrupt the second block programming sequence before the second programming pass of the second block programming sequence is performed;

while the second block programming sequence is interrupted, perform a second DPT operation on the second sample page stack until at least two programming distributions of the first sample page stack are balanced; and

resume the second block programming sequence.