Method of manufacturing a semiconductor device
View Patent ↗In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric field relaxing areas, three of which have in a longitudinal direction three different impurity concentrations decreasing from an N-type high concentration drain region downward, and three of which have in a lateral direction three different impurity concentrations decreasing from the N-type high concentration drain region toward a channel region. An electric field relaxing area that is in contact with the electric field relaxing areas in the longitudinal direction and with the electric field relaxing areas in the lateral direction has the lowest impurity concentration.
1. A method of manufacturing a semiconductor device that comprises an N-channel MOS transistor, the N-channel MOS transistor comprising:
a field oxide film and a gate oxide film formed on a semiconductor substrate;
a gate electrode on the gate oxide film, the gate electrode having a first end extended to the field oxide film;
an N-type high concentration source region at a second end of the gate electrode;
a channel region under the gate oxide film and sandwiched between the N-type high concentration source region and a first end portion of the field oxide film;
an N-type high concentration drain region at a second end portion of the field oxide film opposite from the first end portion of the field oxide film; and
a plurality of electric field relaxing areas under the field oxide film, around the N-type high concentration drain region,
the method comprising:
forming a P-type well region and a first N-type well region on a surface of the semiconductor substrate, the P-type well region and the first N-type well region having an interface therebetween;
forming a second N-type well region in the first N-type well region and in a part of the P-type well region, such that a depth of the second N-type well region is shallower than a depth of the first N-type well region;
forming the field oxide film and an N-type intermediate concentration diffusion region simultaneously by oxidization and diffusion of an N-type impurity introduced by ion implantation under a region where the field oxide film is to be formed, the N-type intermediate concentration diffusion region extending across the interface between the first N-type well region and the P-type well region intermediate to the field oxide film and across the second N-type well region and into the P-type well region, the N-type intermediate concentration diffusion region having a depth shallower than the depth of the second N-type well region, and having an N-type impurity concentration higher than that of the second N-type well region;
forming the channel region in a region where no field oxide film is formed;
forming the gate oxide film on the channel region;
forming the gate electrode on the gate oxide film; and
forming the N-type high concentration source region and the N-type high concentration drain region by ion implantation of an N-type impurity at a high concentration by using the gate electrode and the field oxide film as a mask.
2. A method of manufacturing a semiconductor device according to claim 1 , further comprising:
adjusting a lateral distance (X 1 ) between the channel region and an interface of the second N-type well region and the P-type well region; and
adjusting a lateral distance (X 3 ) between the second N-type well region and the N-type high concentration drain region.
3. A method of manufacturing a semiconductor device according to claim 1 , further comprising:
adjusting a lateral distance (X 2 ) between an interface of the second N-type well region and the P-type well region and the interface between the first N-type well region the P-type well region; and
adjusting a lateral distance (X 3 ) between the second N-type well region and the N-type high concentration drain region.