Obfuscation-enhanced memory encryption
View Patent ↗The present disclosure includes apparatuses and methods for obfuscation-enhanced memory encryption. An example method comprises performing a write operation, wherein the write operation includes transmitting a number of write transactions received from a host along with a number of spurious transactions to a memory, and wherein the number of spurious transactions are transmitted at a particular rate among the number of received write transactions.
1. A method of operating memory, comprising:
reordering a number of write transactions received from a host via a host interface;
performing a write operation of the number of reordered write transactions along with a number of spurious transactions to a memory, wherein the number of reordered write transactions are executed in a different sequence than a particular sequence in which they were received via the host interface.
2. The method of claim 1 , further comprising, subsequent to performing the write operation of the number of reordered write transactions along with the number of spurious transactions to the memory:
retrieving a number of read transactions corresponding to the number of reordered write transactions previously written to the memory;
reordering the number of read transactions retrieved from the memory to a same sequence in which the corresponding number of write transactions were received via the host interface; and
returning the number of reordered read transactions to the host.
3. The method of claim 2 , further comprising discarding the number of spurious transactions among the number of read transactions prior to returning the number of read transactions to the host.
4. The method of claim 1 , further comprising using previously written data values for generating the number of spurious transactions such that at least a portion of data values of the number of spurious transactions corresponds to the previously written data values.
5. The method of claim 1 , wherein the method includes encrypting addresses and data corresponding to the number of write transactions using at least one of an electronic code book (ECB) and a pseudo counter mode (PCTR) technique.
6. The method of claim 1 , further comprising generating the number of spurious transactions at a particular rate.
7. The method of claim 6 , further comprising adjusting the particular rate, during operation, to increase or decrease security associated with the number of write transactions.
8. The method of claim 7 , further comprising tracking locality of write addresses of the number of write transactions and adjusting the particular rate responsive to determining repetitive writes to a same address and/or address range reaches a threshold value.
9. A system, comprising:
a host; and
a controller coupled to the host and a memory, the controller configured to:
retrieve, in a first sequence, a number of read transactions from the memory along with a number of spurious transactions among the number of read transactions;
reorder the number of retrieved read transactions to a second sequence that is different than the second sequence; and
return, in the second sequence, the number of reordered read transactions to the host.
10. The system of claim 9 , wherein the number of read transactions are retrieved from the memory responsive to receipt of a read request from the host.
11. The system of claim 9 , wherein the number of read transactions retrieved from the memory corresponds to a number of write transactions received, in the first sequence, from the host, and previously written, in the second sequence, to the memory.
12. The system of claim 9 , wherein the number of read transactions stored in the memory are encrypted transactions, and the controller is configured to decrypt the number of encrypted read transactions prior to returning to the host.
13. The system of claim 9 , wherein the controller is configured to reorder the number of read transactions independently from the host.
14. The system of claim 9 , wherein the controller is configured to:
receive a number of write transactions from the host via a host interface;
reorder the number of write transactions without inserting a number of spurious transactions to the number of write transactions; and
perform a write operation of the number of reordered write transactions to the memory, wherein the number of reordered write transactions are executed in a different sequence than a particular sequence in which they were received via the host interface.
15. The system of claim 9 , wherein the controller is configured to generate the number of spurious transactions independently from the host.
16. A system, comprising:
a host; and
a controller coupled to the host and a memory, the controller configured to:
receive a number of write transactions from the host via a host interface;
reorder the number of write transactions to a different sequence than a particular sequence in which they were received via the host interface;
insert a number of spurious transactions among the number of reordered write transactions; and
perform a write operation of the number of reordered write transactions along with the number of inserted spurious transactions to the memory.
17. The system of claim 16 , wherein the controller is configured to reorder the number of write transactions independently from the host.
18. The system of claim 16 , wherein the controller is configured to generate the number of spurious transactions independently from the host.
19. The system of claim 16 , wherein the memory is a non-volatile and byte-addressable memory.
20. The system of claim 16 , wherein the controller is configured to write data corresponding to the number of spurious transactions to a dedicated portion of the memory.