Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.
1. A semiconductor memory device comprising:
a stacked body provided above a substrate, in which conductive layers are isolated from each other and stacked along a first direction crossing a surface of the substrate;
a source layer provided between the substrate and the stacked body;
memory pillars that extend through the stacked body along the first direction and are coupled to the source layer;
a first insulation film provided above the memory pillars;
an isolation region provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, the isolation region isolating the stacked body in a second direction crossing the first direction;
a first silicon nitride member provided above the first insulation film;
a second silicon nitride member provided on a side wall of the isolation region; and
through contacts penetrating the first insulation film, the stacked body and the source layer along the first direction, only one through contact of the through contacts being provided to correspond to one hole extending through the stacked body.
2. The semiconductor memory device according to claim 1 ,
wherein each of the memory pillars has a columnar shape extending in the first direction, the isolation region has a plate shape extending in the first direction, and the second silicon nitride member is arranged between the memory pillars and the isolation region.
3. The semiconductor memory device according to claim 1 ,
wherein the first insulation film and the isolation region comprise silicon oxide.
4. The semiconductor memory device according to claim 1 ,
wherein intersections of the memory pillars and the conductive layers respectively function as memory cells.
5. The semiconductor memory device according to claim 1 ,
wherein each of the memory pillars includes a charge storage film, a tunnel insulation film and a semiconductor layer.
6. The semiconductor memory device according to claim 1 ,
further comprising contacts or vias provided on the memory pillars along the first direction in the first insulation film.
7. The semiconductor memory device according to claim 6 ,
wherein upper surfaces of the contacts or vias on the memory pillars are provided at a substantially same height as upper surfaces of the through contacts along the first direction.
8. The semiconductor memory device according to claim 1 ,
further comprising a lower interconnect provided between the substrate and the source layer, one end of the one through contact being connected to the lower interconnect.
9. The semiconductor memory device according to claim 1 ,
further comprising a peripheral circuit provided below the source layer, the through contacts being coupled to the peripheral circuit.
10. The semiconductor memory device according to claim 1 ,
further comprising vias provided on the through contacts, the vias penetrating the first silicon nitride member along the first direction.
11. The semiconductor memory device according to claim 1 ,
wherein the through contacts include tungsten.
12. The semiconductor memory device according to claim 10 ,
wherein the vias include tungsten.