Apparatuses and methods for compute enabled cache

1. An apparatus, comprising:

a memory configured to store cache data and having:

a memory array;

a sensing circuitry comprising a plurality of sense amplifiers and a plurality of compute components to perform logical operations; and

a controller coupled to the memory array, the controller configured to:

create a block select as metadata to a cache line to control alignment of cache blocks within the memory array; and

create a subrow select as metadata to the cache line to control placement of the cache line on a particular row in the memory array to align the cache line to one or more of the plurality of sense amplifiers.

2. The apparatus of claim 1 , wherein the memory is a last layer cache (LLC) memory.

3. The apparatus of claim 2 , wherein the plurality of sense amplifiers are configured to access and to operate on cached data in the LLC memory without moving the cached data to a higher level in the memory.

4. The apparatus of claim 1 , wherein:

the block select enables an offset to the cache line; and

the subrow select enables multiple sets to a set associative cache.

5. The apparatus of claim 1 , wherein the block select provides an offset to a page in a dynamic random access memory (DRAM) page.

6. The apparatus of claim 1 , wherein the controller is configured to:

change the block select and the subrow select;

relocate the cached data transparently to a host processor; and

wherein the block select and the subrow select are not part of an address space of the host processor.

7. The apparatus of claim 6 , wherein the memory controller is configured to store a copy of the block select and the subrow select internal to the host processor.

8. The apparatus of claim 1 , wherein the memory controller is configured to:

use the block select to control alignment of cached data in the memory array in the memory; and

use the subrow select to control resource allocation in the memory array.

9. An apparatus, comprising:

a memory device comprising:

an array of memory cells;

sensing circuitry coupled to the array; and

a controller coupled to the array and sensing circuitry and configured to:

receive a cache line having block select and subrow select metadata; and

operate on the block select and subrow select metadata to:

control alignment of cache blocks in the array; and

allow the cache line to be placed on a particular row of the array to align the cache line to the sensing circuitry.

10. The apparatus of claim 9 , wherein the apparatus further includes a cache controller to:

create the block select metadata and insert to the cache line; and

create the subrow select metadata and insert to the cache line.

11. The apparatus of claim 9 , wherein the block select metadata and the row select metadata are stored internal to the memory device and are transparent to an address space of a processing resource of the host.

12. The apparatus of claim 9 , wherein each cache line is handled as multiple vectors of different bit length values.

13. The apparatus of claim 12 , wherein each of the different bit length values of the multiple vectors is further subdivided into multiple elements.

14. The apparatus of claim 13 , wherein the controller is configured to use the subrow select metadata to select a subarray to place an element of the multiple elements of a vector.

15. The apparatus of claim 9 , wherein the controller is configured to:

store the cache block in the array; and

retrieve a cache line to perform logical operations with the plurality of compute components and the plurality of sense amplifiers.

16. A method for operating a cache memory, comprising:

creating a block select as metadata to a cache line to control alignment of cache blocks in a memory array of the cache memory comprising sensing circuitry including a plurality of sense amplifiers and a plurality of compute components to perform logical operations; and

creating a subrow select as metadata to the cache line to control placement of at least a portion of the cache line on multiple rows in the memory array.

17. The method of claim 16 , wherein the method comprises:

receiving the block select and the subrow select to a memory controller in a processing in memory (PIM) device, the memory array is a dynamic random access memory (DRAM) array, wherein the PIM device comprises:

the sensing circuitry coupled to the memory array, the sensing circuitry including the plurality of sense amplifiers and the plurality of compute components configured to implement logical operations;

storing the cache block in the memory array; and

retrieving at least a portion of the cache line to perform logical operations with the plurality of compute components and the plurality of sense amplifiers.

18. The method of claim 16 , further comprising:

using the block select to choose which part of a row in the memory array having a first bit width to access as a chunk having a second bit width as part of an array access request;

using the block select and the subrow select in a repeated manner to allow a cache line to be split and placed differently in a bank of the memory array.

19. The method of claim 18 , wherein the memory array is in a processing in memory (PIM) based device and further comprising:

placing a plurality of different cache blocks in a plurality of different banks in a dynamic random access memory (DRAM) to allow multiple mapped single cache lines.

20. The method of claim 19 , further comprising managing a first bit length cache line on a second bit length interface such that multiple second bit length chunks can each have a different alignment.