IP Library Granted Patent US 10,262,745
Granted Patent B2
US 10,262,745 · App. 16/130,324 · Granted Apr 16, 2019

Apparatuses and methods using dummy cells programmed to different states

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Quick Facts
Patent No.
US 10,262,745
App. No.
16/130,324
Granted
Apr 16, 2019
Kind
B2
Abstract

Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.

Claims (49)

1. An apparatus, comprising:

a plurality of word lines;

a plurality of memory strings coupled to the plurality of word lines, wherein each string of the plurality of memory strings includes a plurality of memory cells configured to store user data, and further includes a plurality of memory cells configured to be activated based on whether a memory cell of the plurality of memory cells configured to store user data is selected; and

a control unit configured to provide a read voltage to a word line of the plurality of word lines corresponding to a selected memory cell of the plurality of memory cells configured to store user data.

2. The apparatus of claim 1 , wherein the control unit is further configured to provide a pass voltage to at least one word line of the plurality of word lines.

3. The apparatus of claim 1 , wherein the control unit is further configured to provide a pass voltage to at least one word line of the plurality of word lines corresponding to at least one respective unselected memory cell of the plurality of memory cells configured to store user data.

4. The apparatus of claim 1 , wherein a string of the plurality of memory strings includes first memory cells of the plurality of memory cells configured to store user data,

wherein the first memory cells include the selected memory cell,

wherein the string further includes second memory cells of the plurality of memory cells configured to be activated based on whether a memory cell of the plurality of memory cells configured to store user data is selected, and

wherein the control unit is further configured to deactivate one of the second memory cells.

5. The apparatus of claim 1 , wherein a string of the plurality of memory strings includes first memory cells of the plurality of memory cells configured to store user data,

wherein the first memory cells include the selected memory cell,

wherein the string further includes second memory cells of the plurality of memory cells configured to be activated based on whether a memory cell of the plurality of memory cells configured to store user data is selected, and

wherein the control unit is further configured to activate one of the second memory cells.

6. The apparatus of claim 1 , wherein a string of the plurality of memory strings includes first memory cells of the plurality of memory cells configured to store user data,

wherein the first memory cells include the selected memory cell,

wherein the string fur includes second memory cells of the plurality of memory cells configured to be activated based on whether a memory cell of the plurality of memory cells configured to store user data is selected, and each of the second memory cells includes a corresponding threshold voltage, and

wherein the control unit is further configured to provide control signals to the second memory cells to couple the first memory cells to a source, and the control signals provided to the second memory cells include at least one corresponding voltage greater than at least one of the corresponding threshold voltages of the second memory cells, respectively.

7. The apparatus of claim 1 , wherein a string of the plurality of memory strings includes respective memory cells of the plurality of memory cells configured to store user data, and

wherein the string further includes a dram select gate coupled in series with the respective memory cells configured to store user data.

8. The apparatus of claim 1 , wherein a string of the plurality of memory strings includes respective memory cells of the plurality of memory cells configured to store user data, and

wherein the string further includes a source select gate coupled in series with the respective memory cells configured to store user data.

9. The apparatus of claim 1 , wherein a memory cell of the plurality of memory cells is configured to be activated based on whether a memory cell of the plurality of memory cells configured to store user data is selected has a programmed threshold voltage.

10. The apparatus of claim 1 , wherein a string of the plurality of memory strings includes respective memory cells of the plurality of memory cells configured to store user data, and

wherein the string further includes a source select gate and a drain select gate coupled in series with the respective memory cells configured to store user data.

11. A method, comprising:

determining a selected memory cell of a plurality of memory cells in a memory string, wherein the plurality of memory cells include more than one memory cell configured to store user data and more than one memory cell configured to not store user data, and wherein the selected memory cell is one of the more than one memory cell configured to store user data;

providing a read voltage to a word line of a plurality of word lines, the word line corresponding to the selected memory cell; and

providing a pass voltage to at least one word line of the plurality of word lines corresponding to at least one respective unselected memory cell of the plurality of memory cells configured to store user data.

12. The method of claim 11 , wherein memory cells of the more than one memory cell configured to not store user data have respective programmed threshold voltages.

13. The method of claim 11 , further comprising:

deactivating a memory cell of the more than one memory cell configured to not store user data.

14. The method of claim 11 , further comprising:

activating a memory cell of the more than one memory cell configured to not store user data.

15. The method of claim 11 , further comprising:

activating a first memory cell of another more than one memory cell in another memory string, the another more than one memory cell configured to not store user data; and

deactivating a second memory cell of the another more than one memory cell.

16. The method of claim 11 , further comprising:

providing during a memory access operation control signals to activate a first memory cell of the more than one memory cell configured to not store user data, and to deactivate a second memory cell of the more than one memory cell configured to not store user data.

17. An apparatus, comprising:

a plurality of word lines;

a plurality of memory strings, wherein each string of the memory strings includes a plurality of memory cells coupled, respectively, to the plurality or word lines, and wherein the plurality of memory cells include more than one first memory cells configured to store user data and more than one second memory cells configured to not store user data; and

a control unit configured to provide a pass voltage to at least one word line of the plurality of word lines corresponding to at least one unselected memory cell of the more than one first memory cells.

18. The apparatus of claim 17 , wherein the plurality of memory strings include an unselected string, and the unselected string includes respective memory cells of the more than one second memory cells, and

wherein the control unit is further configured to provide during a memory access operation a control signal to activate a memory cell of the respective memory cells in the unselected string configured to not store user data.

19. The apparatus of claim 17 , wherein the plurality of memory strings include an unselected string, and the unselected string includes respective memory cells of the more than one second memory cells, and

wherein the control unit is further configured to provide during a memory access operation a control signal to activate a first memory cell of the respective memory cells in the unselected string configured to not store user data, and deactivate a second memory cell of the respective memory cells in the unselected string configured to not store user data.

20. The apparatus of claim 17 , wherein the plurality of memory strings include an unselected string, and the unselected string includes respective memory cells of the more than one second memory cells, and

wherein the control unit is further configured to provide during a memory access operation a control signal to deactivate a memory cell of the respective memory cells in the unselected string configured to not store user data to float a channel of the unselected string.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051028/0835 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050719/0550 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.., AS COLLATERAL AGENT
Reel/Frame 047630/0756 →
SUPPLEMENT NO. 10 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048102/0420 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2018
From: TANZAWA, TORU; YIP, AARON
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046868/0211 →