Transient Sensing of Memory Cells
The present invention is directed to a method for sensing the resistance state of a memory cell, which includes a memory element and a selection transistor coupled in series between first and second conductive lines. The method includes the steps of precharging the first conductive line; allowing the voltage of the first conductive line to decay toward zero by discharging through the second conductive line; measuring the voltage of the first conductive line after a discharge period to determine the resistance state of the memory cell; concluding that the memory cell is in the high resistance state if the measured voltage is greater than a reference level; and concluding that the memory cell is in the low resistance state if the measured voltage is less than the reference level. The discharge period is shorter than a time period required for the voltage of the first conductive line to reach zero.
1 . A method for sensing a resistance state of a memory cell, which includes a memory element and a transistor coupled in series between first and second conductive lines, the method comprising the steps of:
precharging at least the first conductive line to a first voltage;
allowing a voltage of the first conductive line to decay by discharging through the second conductive line;
measuring the voltage of the first conductive line after a discharge period to determine the resistance state of the memory cell;
concluding that the memory cell is in a high resistance state if the measured voltage is greater than a reference level; and
concluding that the memory cell is in a low resistance state if the measured voltage is less than the reference level,
wherein the discharge period is shorter than a time period required for the voltage of the first conductive line to reach zero when the memory cell is in the high resistance state.
2 . The method of claim 1 , wherein the first conductive line has a higher precharged potential than the second conductive line.
3 . The method of claim 1 , wherein the step of allowing a voltage of the first conductive line to decay is accomplished by grounding the second conductive line.
4 . The method of claim 1 , wherein the step of precharging includes precharging the second conductive line.
5 . The method of claim 1 , wherein the step of allowing a voltage of the first conductive line to decay is accomplished by biasing the second conductive line to a negative potential.
6 . The method of claim 1 , wherein the memory element includes a magnetic tunnel junction (MTJ).
7 . The method of claim 1 , wherein the discharge period is shorter than or equal to a time period required for the voltage of the first conductive line to reach zero when the memory cell is in the low resistance state.
8 . A method for sensing a resistance state of a memory cell, which includes a memory element and a transistor coupled in series between first and second conductive lines with the first conductive line connected to a sense amplifier, the method comprising the steps of:
precharging the sense amplifier to a first voltage;
allowing a voltage of the sense amplifier to decay by discharging through the second conductive line;
measuring the voltage of the sense amplifier after a discharge period to determine the resistance state of the memory cell;
concluding that the memory cell is in a high resistance state if the measured voltage is greater than a reference level; and
concluding that the memory cell is in a low resistance state if the measured voltage is less than the reference level,
wherein the discharge period is shorter than a time period required for the voltage of the sense amplifier to reach zero when the memory cell is in the high resistance state.
9 . The method of claim 8 further comprising the step of precharging the first conductive line to a second voltage that is lower than the first voltage before the step of allowing a voltage of the sense amplifier to decay.
10 . The method of claim 8 , wherein the step of allowing a voltage of the first conductive line to decay is accomplished by grounding the second conductive line.
11 . The method of claim 8 , wherein the memory element includes a magnetic tunnel junction (MTJ).
12 . The method of claim 8 , wherein the discharge period is shorter than or equal to a time period required for the voltage of the sense amplifier to reach zero when the memory cell is in the low resistance state.