IP Library Granted Patent US 10,416,694
Granted Patent B2
US 10,416,694 · App. 16/131,472 · Granted Sep 17, 2019

Regulator circuit

Inventors: Takashi Ono (Osaka, JP); Reiji Mochida (Osaka, JP)
Assignee: Panasonic Intellectual Property Management Co., Ltd.
G05F1/565G05F1/56G05F1/575G05F1/59
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Quick Facts
Patent No.
US 10,416,694
App. No.
16/131,472
Granted
Sep 17, 2019
Kind
B2
Abstract

A regulator circuit includes: a voltage detection circuit that detects a magnitude of an output voltage of an output node, and outputs a feedback voltage that indicates a result of the detection; an error amplifier circuit that compares the feedback voltage with a reference voltage, and outputs a voltage that indicates a result of the comparison; an output circuit that supplies an output current to the output node according to the voltage output by the error amplifier circuit; a current detection circuit that detects a magnitude of the output current; and a current bias circuit that supplies an output bias current to the output node, and increases or decreases the output bias current based on a result of the detection of the current detection circuit.

Claims (62)

1. A regulator circuit comprising:

a voltage detection circuit that detects a magnitude of an output voltage of an output node, and outputs a feedback voltage that indicates a result of the detection;

an error amplifier circuit that compares the feedback voltage with a reference voltage, and outputs a voltage that indicates a result of the comparison;

an output circuit that supplies an output current to the output node according to the voltage output by the error amplifier circuit;

a current detection circuit that detects a magnitude of the output current; and

a current bias circuit that supplies an output bias current to the output node, and increases or decreases the output bias current based on a result of the detection of the current detection circuit, wherein:

the current detection circuit outputs a detection current that is proportional to the output current,

the current bias circuit includes a current source that allows a constant current to flow therethrough,

the constant current that flows through the current source is a sum of a first current and a second current, and

the current bias circuit includes:

a first current mirror that receives an input of the detection current as a reference current, and outputs the first current as a mirror current; and

a second current mirror that receives the second current as a reference current, and outputs the output bias current as a mirror current.

2. The regulator circuit according to claim 1 ,

wherein the current detection circuit has a same configuration as a configuration of the output circuit except that a current driving capability is different, and outputs the detection current that is proportional to the magnitude of the output current according to the voltage output by the error amplifier circuit.

3. The regulator circuit according to claim 1 ,

wherein the current detection circuit is provided in parallel to the output circuit.

4. A regulator circuit comprising:

a voltage detection circuit that detects a magnitude of an output voltage of an output node, and outputs a feedback voltage that indicates a result of the detection;

an error amplifier circuit that compares the feedback voltage with a reference voltage, and outputs a voltage that indicates a result of the comparison;

an output circuit that supplies an output current to the output node according to the voltage output by the error amplifier circuit;

a current detection circuit that detects a magnitude of the output current; and

a current bias circuit that supplies an output bias current to the output node, and increases or decreases the output bias current based on a result of the detection of the current detection circuit, wherein:

the current detection circuit outputs a detection current that is proportional to the output current,

the current bias circuit includes a current source that allows a constant current to flow therethrough,

the constant current that flows through the current source is a sum of the detection current and a second current, and

the current bias circuit includes a current mirror that receives the second current as a reference current, outputs a mirror current that is proportional to the second current, is connected to the output node, and supplies a sum of the second current and the mirror current to the output node as the output bias current.

5. The regulator circuit according to claim 4 ,

wherein the current bias circuit includes a clamp circuit that is provided in a wire that transmits the detection current from the current detection circuit to the current source, and limits a voltage of a portion of the wire that is on a side of the current source such that the voltage of the portion of the wire does not exceed the output voltage.

6. The regulator circuit according to claim 4 ,

wherein the current detection circuit has a same configuration as a configuration of the output circuit except that a current driving capability is different, and outputs the detection current that is proportional to the magnitude of the output current according to the voltage output by the error amplifier circuit.

7. The regulator circuit according to claim 4 ,

wherein the current detection circuit is provided in parallel to the output circuit.

8. A regulator circuit comprising:

a voltage detection circuit that detects a magnitude of an output voltage of an output node, and outputs a feedback voltage that indicates a result of the detection;

an error amplifier circuit that compares the feedback voltage with a reference voltage, and outputs a voltage that indicates a result of the comparison;

an output circuit that supplies an output current to the output node according to the voltage output by the error amplifier circuit;

a current detection circuit that detects a magnitude of the output current; and

a current bias circuit that supplies an output bias current to the output node, and increases or decreases the output bias current based on a result of the detection of the current detection circuit,

wherein the current bias circuit includes:

a first current source that includes a first terminal and a second terminal, the first terminal being connected to an arbitrary power supply node or ground node;

a first current mirror that includes an input terminal to receive a reference current, which is connected to an output terminal of the current detection circuit, and an output terminal to output a mirror current, which is connected to the second terminal of the first current source; and

a second current mirror that includes an input terminal to receive a reference current, which is connected to the second terminal of the first current source, and an output terminal to output a mirror current, which is connected to the output node.

9. The regulator circuit according to claim 8 ,

wherein the current detection circuit has a same configuration as a configuration of the output circuit except that a current driving capability is different, and outputs the detection current that is proportional to the magnitude of the output current according to the voltage output by the error amplifier circuit.

10. The regulator circuit according to claim 8 ,

wherein the current detection circuit is provided in parallel to the output circuit.

11. A regulator circuit comprising:

a voltage detection circuit that detects a magnitude of an output voltage of an output node, and outputs a feedback voltage that indicates a result of the detection;

an error amplifier circuit that compares the feedback voltage with a reference voltage, and outputs a voltage that indicates a result of the comparison;

an output circuit that supplies an output current to the output node according to the voltage output by the error amplifier circuit;

a current detection circuit that detects a magnitude of the output current; and

a current bias circuit that supplies an output bias current to the output node, and increases or decreases the output bias current based on a result of the detection of the current detection circuit, wherein:

the current detection circuit outputs a detection current that is proportional to the output current, and

the current bias circuit includes:

a second current source that includes a third terminal that is connected to an arbitrary power supply node or ground node, and a fourth terminal that is connected to an output terminal of the current detection circuit to receive the detection current; and

a current mirror that includes an input terminal to receive a reference current, which is connected to the fourth terminal of the second current source, an output terminal to output a mirror current, which is connected to an arbitrary power supply node or ground node, and a source that is connected to the output node.

12. The regulator circuit according to claim 11 ,

wherein the current bias circuit further includes a clamp circuit that includes a first input terminal that is connected to the output terminal of the current detection circuit, a second input terminal that is connected to the output node, and a first output terminal that is connected to the fourth terminal of the second current source and the input terminal of the current mirror, the clamp circuit being configured to limit a potential of the first output terminal.

13. The regulator circuit according to claim 11 ,

wherein the current detection circuit has a same configuration as a configuration of the output circuit except that a current driving capability is different, and outputs the detection current that is proportional to the magnitude of the output current according to the voltage output by the error amplifier circuit.

14. The regulator circuit according to claim 11 ,

wherein the current detection circuit is provided in parallel to the output circuit.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0870 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2019
From: ONO, TAKASHI; MOCHIDA, REIJI
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 048245/0068 →