IP Library Granted Patent US 10,983,724
Granted Patent B2
US 10,983,724 · App. 16/132,096 · Granted Apr 20, 2021

Controller with distributed sequencer components

Inventors: Jiangli Zhu (San Jose, CA); Cheng Yuan Wu (Fremont, CA); Ying Yu Tai (Mountain View, CA)
Assignee: Micron Technology, Inc.
G06F3/0659G06F3/0604G06F3/0679G06F3/067
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Quick Facts
Patent No.
US 10,983,724
App. No.
16/132,096
Granted
Apr 20, 2021
Kind
B2
Abstract

A host operation to be performed can be received. Sub-operations that are associated with the received host operation can be determined. A memory component of multiple memory components can be identified for each sub-operation. Furthermore, each sub-operation can be transmitted to a media sequencer component that is associated with a respective memory component of the memory components.

Claims (49)

1. A system comprising:

a plurality of memory components; and

a memory sub-system controller operatively coupled with the plurality of memory components, the memory sub-system controller comprising:

a first media sequencer component,

a second media sequencer component, and

a command manager component, the command manager component operatively coupled with the first media sequencer component and the second media sequencer component, to:

receive a host operation to be performed at the system;

determine a plurality of sub-operations associated with the host operation, each sub-operation corresponding to a different one of the plurality of memory components;

identify a corresponding memory component of the plurality of memory components for each sub-operation of the plurality of sub-operations, wherein each corresponding memory component is associated with a different channel of a plurality of channels of the memory sub-system controller, and wherein each of the first media sequencer component and the second media sequencer component is associated with a different channel of the plurality of channels;

transmit a first sub-operation of the plurality of sub-operations to the first media sequencer component that is associated with a first memory component of the plurality of memory components, wherein the first media sequencer component is to determine first page operations for the first memory component based on the first sub-operation; and

transmit a second sub-operation of the plurality of sub-operations to the second media sequencer component that is associated with a second memory component of the plurality of memory component, wherein the second media sequencer component is to determine second page operations for the second memory component based on the second sub-operation.

2. The system of claim 1 , wherein each of the first page operations and the second page operations corresponds to a portion of data specified by the host operation.

3. The system of claim 1 , further comprising:

a plurality of media sequencer components comprising at least the first media sequence component and the second media sequence component, wherein each media sequencer component of the plurality of media sequencer components is associated with a different channel of the plurality of channels.

4. The system of claim 3 , further comprising:

a plurality of error correction components, wherein each error correction component is included in a different channel of the plurality of channels.

5. The system of claim 1 , wherein the command manager component is to further identify the respective memory component of the plurality of memory components for each sub-operation based on a type of the respective memory component, wherein the plurality of memory components correspond to a plurality of types of memory components, and wherein a respective media sequencer component that is associated with the respective memory component of the plurality of memory components schedules the sub-operation based on the type of the respective memory component.

6. A system comprising:

a plurality of memory components;

a command manager component, operatively coupled with the plurality of memory components, to:

receive a host operation to be performed at the system;

determine a plurality of sub-operations associated with the host operation;

identify a memory component of the plurality of memory components for each sub-operation of the plurality of sub-operations; and

transmit each sub-operation of the plurality of sub-operations to a media sequencer component that is associated with a respective memory component of the plurality of memory components;

a plurality of media sequencer components, wherein each media sequencer component of the plurality of media sequencer components is associated with a different channel of a controller of the system; and

a plurality of error correction components, wherein each error correction component is included in a different channel of the controller, wherein each error correction component of the plurality of error correction components generates a particular code word at each memory component of the plurality of memory components that is controlled by a particular channel.

7. The system of claim 6 , wherein each of the page operations corresponds to a portion of data specified by the host operation.

8. The system of claim 6 , wherein the command manager component is to further identify the respective memory component of the plurality of memory components for each sub-operation based on a type of the respective memory component, wherein the plurality of memory components correspond to a plurality of types of memory components, and wherein the media sequencer component that is associated with the respective memory component of the plurality of memory components schedules the sub-operation based on the type of the respective memory component.

9. A system comprising:

a plurality of memory components; and

a memory sub-system controller operatively coupled with the plurality of memory components, the memory sub-system controller comprising:

a command manager component to receive a host operation associated with data at the plurality of memory components and to determine a plurality of sub-operations of the received host operation, each sub-operation corresponding to a different one of the plurality of memory components, and

a plurality of media sequencer components to receive the plurality of sub-operations, wherein each media sequencer component of the plurality of media sequencer components generates one or more page operations for a corresponding memory component of the plurality of memory components based on a received sub-operation of the plurality of sub-operations, wherein each corresponding memory component is associated with a different channel of a plurality of channels of the memory sub-system controller, and wherein each of the plurality of media sequencer components is associated with a different channel of the plurality of channels.

10. The system of claim 9 , wherein each of the one or more page operations corresponds to a portion of the data.

11. The system of claim 9 , further comprising:

a plurality of error correction components, wherein each error correction component is associated with a different media sequencer component.

12. The system of claim 11 , wherein each error correction component of the plurality of error correction components generates a particular code word at each memory component of the plurality of memory components that is controlled by a particular channel of the plurality of channels.

13. The system of claim 9 , wherein the plurality of sub-operations are based on different types of memory components of the plurality of memory components.

14. The system of claim 9 , wherein the data is a first size, wherein second data for a particular sub-operation is at a second size that is smaller than the first size, and wherein third data for a particular page operation is at a third size that is smaller than the second size.

15. A method comprising:

receiving a host operation to be performed;

determining a plurality of sub-operations associated with the host operation;

identifying a memory component of a plurality of memory components for each sub-operation of the plurality of sub-operations;

transmitting, by a processing device, each sub-operation of the plurality of sub-operations to a corresponding media sequencer component that is associated with a respective memory component of the plurality of memory components, wherein each corresponding media sequencer component is one of a plurality of media sequencer components of a memory sub-system controller operatively coupled with the plurality of memory components, wherein each corresponding memory component is associated with a different channel of a plurality of channels of the memory sub-system controller, and wherein each of the plurality of media sequencer components is associated with a different channel of the plurality of channels; and

determining, by the corresponding media sequencer component, page operations for the respective particular memory component that is associated with the corresponding media sequencer component.

16. The method of claim 15 , wherein each of the page operations corresponds to a portion of data specified by the host operation.

17. The method of claim 15 , wherein each of the page operations is associated with a page that corresponds to a smallest unit of a particular memory component that is to be addressed.

18. The method of claim 15 , wherein the identifying of the memory component is based on a type of memory of the memory component.

19. The method of claim 15 , wherein the corresponding media sequencer component is associated with an error correction operation.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051028/0835 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050719/0550 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.., AS COLLATERAL AGENT
Reel/Frame 047630/0756 →
SUPPLEMENT NO. 10 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048102/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE DOCKET NUMBER PREVIOUSLY RECORDED ON REEL 046884 FRAME 0728. ASSIGNOR(S) HEREBY CONFIRMS THE RECORDATION. Recorded Sep 19, 2018
From: ZHU, JIANGLI; WU, CHENG YUAN; TAI, YING YU
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047110/0015 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2018
From: ZHU, JIANGLI; WU, CHENG YUAN; TAI, YING YU
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046884/0728 →