IP Library Granted Patent US 10,756,217
Granted Patent B2
US 10,756,217 · App. 16/132,879 · Granted Aug 25, 2020

Access devices formed with conductive contacts

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Quick Facts
Patent No.
US 10,756,217
App. No.
16/132,879
Granted
Aug 25, 2020
Kind
B2
Abstract

Systems, apparatuses and methods related to access devices formed with conductive contacts are described. An example apparatus may include an access device that includes a field-effect transistor (FET). A vertical pillar may be formed to include a channel of the FET, with a portion of the vertical pillar formed between at least two gates of the FET (i.e., a multi-gate Fin-FET). A conductive contact may be coupled to a body region of the vertical pillar.

Claims (42)

1. An apparatus, comprising:

an access device comprising a field-effect transistor (FET);

a vertical pillar formed to include a channel of the FET, a portion of the vertical pillar formed between at least two gates of the FET (a multi-gate Fin-FET); and

a conductive contact coupled to a body region between the at least two gates positioned on opposite sides of the vertical pillar and within a volume of the vertical pillar determined by areas of the at least two gates.

2. The apparatus of claim 1 , wherein:

the conductive contact is formed from a conductive material; and

the conductive contact is further coupled to a component at a particular bias voltage.

3. The apparatus of claim 1 , wherein the conductive contact is formed from a conductive material that includes at least one of silicon (Si), polycrystalline silicon (polySi), P + Si, P + polySi, germanium (Ge), and Si-Ge (Si 1-x Ge x ).

4. The apparatus of claim 1 , wherein the conductive contact is formed from a conductive material that includes at least one conductive metal.

5. The apparatus of claim 1 , wherein:

the conductive contact is coupled substantially orthogonally to a side surface of the vertical pillar; and

the side surface is substantially parallel to a longitudinal axis of the vertical pillar.

6. The apparatus of claim 1 , wherein:

a storage node is coupled to the access device; and

the storage node and the access device are configured to be operated as a dynamic random access memory (DRAM) cell.

7. The apparatus of claim 1 , wherein the FET of the access device is formed as a metal-oxide semiconductor (MOS).

8. The apparatus of claim 1 , wherein the portion of the vertical pillar is formed between two gates of the multi-gate Fin-FET.

9. The apparatus of claim 1 , wherein the portion of the vertical pillar is formed between three gates of the multi-gate Fin-FET.

10. A system, comprising:

a plurality of dual gate access devices, comprising:

a plurality of trenches formed in a first direction between a corresponding plurality of partitions in an oxide substrate material;

a digit line material to partially fill the plurality of trenches;

an N + polycrystalline silicon (polySi) material formed on the digit line material;

a lightly doped N − material formed on the N + polySi material to fill the plurality of trenches;

a P + polySi material formed as a plurality of conductive contact lines in the first direction on the plurality of partitions; and

a plurality of rails formed from the oxide substrate material in the first direction on a corresponding plurality of the conductive contact lines.

11. The system of claim 10 , wherein the plurality of access devices further comprises:

a plurality of damascene trenches formed in the first direction between a corresponding plurality of the rails; and

a more heavily doped N − polySi material to fill the plurality of damascene trenches.

12. The system of claim 11 , wherein:

the plurality of dual gate access devices further comprises a plurality of trenches formed in a substantially orthogonal second direction;

the plurality of trenches form a plurality of vertical pillars from the more heavily doped N − polySi material in the first direction and the second direction to include channels for a corresponding plurality of the access devices; and

the plurality of vertical pillars are coupled to:

a corresponding plurality of the conductive contact lines; and

the lightly doped N − polySi material in a corresponding plurality of the trenches.

13. The system of claim 12 , wherein the plurality of trenches formed in the second direction extend to an upper surface of the corresponding plurality of the conductive contact lines.

14. The system of claim 12 , wherein the plurality of trenches formed in the second direction extend partially into the corresponding plurality of the conductive contact lines.

15. The system of claim 12 , wherein the plurality of dual gate access devices further comprises:

a gate material formed as separate gates on two opposite surfaces of each of the plurality of vertical pillars in the second direction; and

wherein the gate material is formed:

to couple to the two opposite surfaces of each of the plurality of vertical pillars; and

above the conductive contact lines in order to be uncoupled to the conductive contact lines.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051028/0835 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050719/0550 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.., AS COLLATERAL AGENT
Reel/Frame 047630/0756 →
SUPPLEMENT NO. 10 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048102/0420 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2018
From: LIU, HAITAO; GAO, YUNFEI; KARDA, KAMAL M.; PANDEY, DEEPAK CHANDRA; TANG, SANH D.; YANG, LITAO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046889/0560 →