Memory configurations
View Patent ↗In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack is to store a charge.
1. A memory, comprising:
a group of series-coupled memory cells;
wherein a memory cell of the series-coupled memory cells comprises:
an access gate;
a first control gate and a second control gate coupled to the access gate;
a first dielectric stack between the first control gate and a semiconductor;
a second dielectric stack between the second control gate and the semiconductor;
wherein each of the first and second dielectric stacks is to store a charge and the access gate is between the first dielectric stack and the second dielectric stack; and
wherein the first dielectric stack comprises a first storage dielectric, a first tunneling layer between the first storage dielectric and the semiconductor, a second storage dielectric, and a second tunneling layer between the second storage dielectric and the first storage dielectric.
2. The memory of claim 1 , wherein the first control gate is separate from the second control gate.
3. The memory of claim 1 , wherein the second control gate is below the first control gate.
4. The memory of claim 1 , wherein the first dielectric stack is adjacent to a first conductive region in the semiconductor and the second dielectric stack is adjacent to a second conductive region in the semiconductor.
5. The memory of claim 1 , wherein the first dielectric stack comprises a charge trap adjacent to the second tunnel dielectric, the second storage dielectric adjacent to the charge trap, and a blocking dielectric adjacent to the second storage dielectric.
6. The memory of claim 5 , wherein the first tunnel dielectric comprises OR-SiON, the first storage dielectric comprises i-SRN, the second tunnel dielectric comprises HfSiON, the charge trap comprises GaN, the second storage dielectric comprises i-SRN, and the blocking dielectric comprises HfSiON or HfSiON and AL 2 O 3 .
7. The memory of claim 1 , wherein the first control gate and the second control gate are capacitively coupled to the access gate by a dielectric.
8. The memory of claim 1 , further comprising a gate dielectric between the semiconductor and the access gate.
9. A memory, comprising:
a group of series-coupled memory cells;
wherein each memory cell of the series-coupled memory cells comprises:
an access gate;
a first control gate and a second control gate coupled to the access gate;
a first dielectric stack between the first control gate and a semiconductor; and
a second dielectric stack between the second control gate and the semiconductor;
wherein each of the first and second dielectric stacks is to store a charge and the access gate is between the first dielectric stack and the second dielectric stack;
wherein each of the first and second dielectric stacks comprises first and second charge storage dielectrics and a charge trap between the first and second charge storage dielectrics.
10. The memory of claim 9 , wherein the group of series-coupled memory cells comprises:
a first segment between a first conductive region in the semiconductor adjacent to an upper surface of the semiconductor and a second conductive region in the semiconductor;
a second segment between a third conductive region in the semiconductor adjacent to the upper surface of the semiconductor and the second conductive region;
wherein the second conductive region couples the first and second segments in series.
11. The memory of claim 10 , wherein the first conductive region is coupleable to a data line and the third conductive region is coupleable to a source.
12. The memory of claim 9 , wherein each of the first and second dielectric stacks comprises a tunnel dielectric between the first charge storage dielectric and the charge trap.
13. A method of forming a memory, comprising:
forming a group of series-coupled memory cells;
wherein forming a memory cell of the series-coupled memory cells comprises:
forming a first dielectric stack adjacent to a semiconductor, wherein forming the first dielectric stack comprises:
forming a first storage dielectric,
forming a first tunneling layer between the first storage dielectric and the semiconductor,
forming a second storage dielectric;
forming a second tunneling layer between the second storage dielectric and the first storage dielectric;
forming a second dielectric stack adjacent to the semiconductor;
forming an access gate adjacent to the semiconductor such that the access gate is between the first dielectric stack and the second dielectric stack;
forming a first control gate and a second control gate such that the first control gate and the second control gate are coupled to the access gate and such that first dielectric stack is between the first control gate and the semiconductor and the second dielectric stack is between the second control gate and the semiconductor;
wherein each of the first and second dielectric stacks is to store a charge.
14. The method of claim 13 , further comprising forming the first control gate and the second control gate such that the first control gate is separate from the second control gate.
15. The method of claim 13 , further comprising forming the first control gate and the second control gate such that the second control gate is below the first control gate.
16. The method of claim 13 , further comprising:
forming a first conductive region in the semiconductor adjacent to the first dielectric stack; and
forming a second conductive region in the semiconductor adjacent to the second dielectric stack.
17. The method of claim 13 , wherein forming the first and second dielectric stacks comprises:
forming a first storage dielectric;
forming a charge trap; and
forming a second storage dielectric such that the charge trap is between the first and second storage dielectrics.
18. The method of claim 13 , wherein forming the first and second dielectric stacks comprises:
forming a first tunnel dielectric adjacent to the semiconductor;
forming a first storage dielectric adjacent to the first tunnel dielectric;
forming a second tunnel dielectric adjacent to the first storage dielectric;
forming a charge trap adjacent to the second tunnel dielectric;
forming a second storage dielectric adjacent to the charge trap; and
forming a blocking dielectric adjacent to the second storage dielectric.
19. The method of claim 18 , wherein
forming the first tunnel dielectric comprises forming OR-SiON;
forming the the first storage dielectric comprises forming i-SRN;
forming the second tunnel dielectric comprises forming HfSiON;
forming the charge trap comprises forming GaN;
forming the second storage dielectric comprises forming i-SRN; and
forming the blocking dielectric comprises forming HfSiON or HfSiON and AL 2 O 3 .
20. The method of claim 13 , further comprising forming a dielectric between the first control gate and the access gate and between the second control gate and the access gate such that the first control gate and the second control gate are capacitively coupled to the access gate by the dielectric.