Fault tolerant and diagnostic boot

1. A method for processing data, comprising:

starting a processor from an off state;

loading watchdog timer handler code into a processor memory;

executing the watchdog timer handler code;

determining whether a catastrophic error has occurred during execution of the watchdog timer handler code;

updating error code if it is determined that the catastrophic error has occurred; and

setting up a first stack frame associated with a first phase if it is determined that a catastrophic error has not occurred.

2. The method of claim 1 further comprising:

determining whether an error has occurred during execution of the first stack frame associated with the first phase; and

invoking a watchdog timer handler if the error has occurred during execution of the first stack frame.

3. The method of claim 1 further comprising:

determining whether a minimum boot path exists after execution of the first stack frame associated with the first phase; and

booting the processor using the minimum booth path if the minimum boot path exists.

4. The method of claim 1 further comprising setting up a second stack frame associated with a second phase if it is determined that a catastrophic error has not occurred during the first phase.

5. The method of claim 4 further comprising:

determining whether a minimum boot path exists after execution of the second stack frame associated with the second phase; and

booting the processor using the minimum booth path if the minimum boot path exists.

6. The method of claim 1 further comprising setting up a plurality of additional stack frames if it is determined that a catastrophic error has not occurred during a preceding phase.

7. The method of claim 6 further comprising:

determining whether a minimum boot path exists after execution of a last stack frame associated with a last phase; and

booting the processor using the minimum booth path if the minimum boot path exists.

8. The method of claim 1 further comprising:

determining whether execution of the first phase is complete; and

reinitializing a watchdog timer if execution of the first phase is complete.

9. The method of claim 8 further comprising:

determining whether memory regions are accessible if execution of the first phase is not complete; and

capturing error data if it is determined that the memory regions are not accessible.

10. The method of claim 8 further comprising:

determining whether memory regions are accessible if execution of the first phase is not complete; and

capturing a detailed error if it is determined that the memory regions are accessible.

11. A system for processing data, comprising:

a processor configured to perform predetermined actions when starting from an off state, the actions including:

load watchdog timer handler code into a processor memory;

execute the watchdog timer handler code;

determine whether a catastrophic error has occurred during execution of the watchdog timer handler code;

update error code if it is determined that the catastrophic error has occurred; and

set up a first stack frame associated with a first phase if it is determined that a catastrophic error has not occurred.

12. The system of claim 11 , wherein the processor is further configured to:

determine whether an error has occurred during execution of the first stack frame associated with the first phase; and

invoke a watchdog timer handler if the error has occurred during execution of the first stack frame.

13. The system of claim 11 , wherein the processor is further configured to:

determine whether a minimum boot path exists after execution of the first stack frame associated with the first phase; and

boot the processor using the minimum booth path if the minimum boot path exists.

14. The system of claim 11 wherein the processor is further configured to set up a second stack frame associated with a second phase if it is determined that a catastrophic error has not occurred during the first phase.

15. The system of claim 11 wherein the processor is further configured to:

determine whether a minimum boot path exists after execution of the second stack frame associated with the second phase; and

boot the processor using the minimum booth path if the minimum boot path exists.

16. The system of claim 11 wherein the processor is further configured to set up a plurality of additional stack frames if it is determined that a catastrophic error has not occurred during a preceding phase.

17. The system of claim 16 wherein the processor is further configured to:

determine whether a minimum boot path exists after execution of a last stack frame associated with a last phase; and

boot the processor using the minimum booth path if the minimum boot path exists.

18. The system of claim 11 wherein the processor is further configured to:

determine whether execution of the first phase is complete; and

reinitialize a watchdog timer if execution of the first phase is complete.

19. The system of claim 18 wherein the processor is further configured to:

determine whether memory regions are accessible if execution of the first phase is not complete; and

capture error data if it is determined that the memory regions are not accessible.

20. A method for processing data, comprising:

starting a processor from an off state;

loading watchdog timer handler code into a processor memory;

executing the watchdog timer handler code;

determining whether a catastrophic error has occurred during execution of the watchdog timer handler code;

updating error code if it is determined that the catastrophic error has occurred;

setting up a first stack frame associated with a first phase if it is determined that a catastrophic error has not occurred; and

booting the processor after execution of the first stack frame associated with the first phase.